MOSFET parametric amplifier

Abstract

A circuit includes an input terminal adapted to receive an input voltage, a MOSFET having its drain terminal and its source terminal connected together, a first switching arrangement configured to be controlled by a first clock signal and adapted to selectively couple the gate terminal to the input terminal, and a further switching arrangement configured to be controlled by a further clock signal in timing relationship with the first clock signal and adapted to selectively couple the source terminal and a first voltage which is capable of pulling carriers out of a channel when the first switching arrangement is not coupling the input terminal to the gate terminal.

1 . A circuit including an input terminal adapted to receive an input voltage, the circuit comprising: 
 a MOSFET having a source terminal, a drain terminal, a gate terminal, and a substrate or backgate terminal adapted to be coupled to a substrate voltage source, the drain terminal and the source terminal being connected together;    a first switching arrangement configured to be controlled by a first clock signal, the first switching arrangement being adapted to selectively couple the gate terminal to the input terminal; and    a further switching arrangement configured to be controlled by a further clock signal in timing relationship with the first clock signal, the further switching arrangement being adapted to selectively couple the source terminal and a first voltage which is capable of pulling carriers out of a channel when the first switching arrangement is not coupling the input terminal to the gate terminal.    
   
   
       2 . A circuit including an input terminal adapted to receive an input signal, the circuit comprising: 
 a MOSFET having a source terminal, a drain terminal, a gate terminal, and a substrate terminal adapted to be coupled to a substrate voltage source, the drain terminal and the source terminal being connected together;    a first impedance associated with the input signal electrically coupled to the gate terminal and the input terminal; and    a second impedance associated with a local oscillator signal configured to electrically couple the local oscillator signal and the source terminal.    
   
   
       3 . A circuit including an input terminal adapted to receive an input voltage, the circuit comprising: 
 a MOSFET having a source terminal, a drain terminal, a gate terminal, and a substrate terminal adapted to be coupled to a substrate voltage source, the drain terminal and the source terminal being connected together;    a first switching arrangement configured to be controlled by a first clock signal, the first switching arrangement being adapted to selectively couple the gate terminal to the input terminal; and    a second impedance associated with a local oscillator signal configured to electrically couple the local oscillator signal and the source terminal, whereby the local oscillator signal is capable of modulating a channel charge when the first switching arrangement is not coupling the input terminal to the output terminal.    
   
   
       4 . A circuit including an input terminal adapted to receive an input signal, the circuit comprising: 
 a MOSFET having a source terminal, a drain terminal, a gate terminal, and a substrate terminal adapted to be coupled to a substrate voltage source, the drain terminal and the source terminal being connected together;    a first impedance associated with the input signal electrically coupled to the gate terminal and the input terminal; and    a further switching arrangement configured to be controlled by a further clock signal in timing relationship with the first clock signal, the further switching arrangement being adapted to selectively couple the source terminal and a second voltage which is capable of pulling carriers out of a channel when the first switching arrangement is not coupling the input terminal to the gate terminal.    
   
   
       5 . The circuit of  claim 1  further comprising a second switching arrangement configured to be controlled by a second clock signal in timing relationship with the first clock signal, the second switching arrangement being adapted to selectively couple the source terminal to a second voltage.  
   
   
       6 . The circuit of  claim 1  wherein, the MOSFET is of n-type, the first voltage is ground, and the second voltage is a pulling voltage.  
   
   
       7 . The circuit of  claim 1  wherein, the MOSFET is of p-type, the first voltage is a pulling voltage, and the second voltage is ground.  
   
   
       8 . The circuit of  claim 2 , wherein when the local oscillator signal is introduced, the local oscillator signal is capable of producing a varying voltage at the source terminal which is capable of producing a time varying impedance as seen from the gate terminal, the time varying impedance resulting in mixing of the input signal with the local oscillator signal or harmonics of the local oscillator signal.  
   
   
       9 . The circuit of  claim 2  wherein the first impedance is approximately equal to the output impedance of the input signal.  
   
   
       10 . The circuit of  claim 2 , wherein the second impedance is approximately equal to the output impedance of the local oscillator signal.  
   
   
       11 . The circuit of  claim 3  wherein the second impedance is approximately equal to the output impedance of the local oscillator signal.  
   
   
       12 . The circuit of  claim 3  wherein the first impedance is approximately equal to the output impedance of the input signal.  
   
   
       13 . The circuit of  claim 4  further comprising a second switching arrangement configured to be controlled by a second clock signal, the second switching arrangement being adapted to selectively couple the source terminal to a second voltage.  
   
   
       14 . The circuit of  claim 4  wherein, the MOSFET is of n-type, the first voltage is ground, and the second voltage is a pulling voltage.  
   
   
       15 . The circuit of  claim 4  wherein, the MOSFET is of p-type, the first voltage is a pulling voltage, and the second voltage is ground.  
   
   
       16 . A mixer circuit comprising the circuit of  claim 1 .  
   
   
       17 . A mixer circuit comprising the circuit of  claim 2 .  
   
   
       18 . A mixer circuit comprising the circuit of  claim 3 .  
   
   
       19 . A mixer circuit comprising the circuit of  claim 4 .  
   
   
       20 . The circuit of  claim 1  further comprising: 
 a diode or transistor having a first and a second terminal, the first terminal configured to be coupled to the gate terminal; and    a capacitor configured to be coupled to the second terminal of the diode.    
   
   
       21 . The circuit of  claim 2  further comprising: 
 a diode or transistor having a first and a second terminal, the first terminal configured to be coupled to the gate terminal; and    a capacitor configured to be coupled to the second terminal of the diode.    
   
   
       23 . The circuit of  claim 3  further comprising: 
 a diode or transistor having a first and a second terminal, the first terminal configured to be coupled to the gate terminal; and    a capacitor configured to be coupled to the second terminal of the diode.    
   
   
       24 . The circuit of  claim 4  further comprising: 
 a diode or transistor having a first and a second terminal, the first terminal configured to be coupled to the gate terminal; and    a capacitor configured to be coupled to the second terminal of the diode.    
   
   
       25 . The circuit of  claim 1  further comprising: 
 an additional switching arrangement having a first and a second terminal, the first terminal configured to be coupled to the gate terminal; and    a capacitor configured to be coupled to the second terminal of the diode.    
   
   
       26 . The circuit of  claim 2  further comprising: 
 an additional switching arrangement having a first and a second terminal, the first terminal configured to be coupled to the gate terminal; and    a capacitor configured to be coupled to the second terminal of the diode.    
   
   
       27 . The circuit of  claim 3  further comprising: 
 an additional switching arrangement having a first and a second terminal, the first terminal configured to be coupled to the gate terminal; and    a capacitor configured to be coupled to the second terminal of the diode.    
   
   
       28 . The circuit of  claim 4  further comprising: 
 an additional switching arrangement having a first and a second terminal, the first terminal configured to be coupled to the gate terminal; and    a capacitor configured to be coupled to the second terminal of the diode.    
   
   
       29 . A charge pump circuit comprising the circuit of  claim 1 .  
   
   
       30 . A charge pump circuit comprising the circuit of  claim 2 .  
   
   
       31 . A charge pump circuit comprising the circuit of  claim 3 .  
   
   
       32 . A charge pump circuit comprising the circuit of  claim 4 .  
   
   
       33 . A circuit including an input terminal adapted to receive a first and second input voltage, the circuit comprising: 
 a first MOSFET having a first source terminal, a first drain terminal, a first gate terminal, and a first substrate terminal adapted to be coupled to a first substrate voltage source, the first drain terminal and the first source terminal being connected together;    a first switching arrangement configured to be controlled by a first clock signal, the first switching arrangement being adapted to selectively couple the first gate terminal and the first input terminal;    a further switching arrangement configured to be controlled by a further clock signal in timing relationship with the first clock signal, the further switching arrangement being adapted to selectively couple the first source terminal and a first voltage which is capable of pulling carriers out of a channel when the first switching arrangement is not coupling the input terminal and the gate terminal;    a second MOSFET having a second source terminal, a second drain terminal, a second gate terminal, and a second substrate terminal adapted to be coupled to a second substrate voltage source, the second drain terminal and the first source terminal being connected together;    a second switching arrangement configured to be controlled by a second clock signal, the second switching arrangement being adapted to selectively couple the second gate terminal and the second input terminal;    a second further switching arrangement configured to be controlled by a second further clock signal in timing relationship with the second clock signal, the second further switching arrangement being adapted to selectively couple the second source terminal and a second voltage which is capable of pulling carriers out of a channel when the second switching arrangement is not coupling the input terminal and the gate terminal; and    a third switching arrangement configured to be controlled by a third clock signal in timing relationship with the first clock signal, the third switching arrangement being adapted to selectively couple the first gate terminal and the second gate terminal when the first switching arrangement is not coupling the first gate terminal with the first input terminal and the second gate terminal is not coupling the second gate terminal with the second input terminal.    
   
   
       34 . A finite impulse response filter comprising the circuit of  claim 1 .  
   
   
       35 . A finite impulse response filter comprising the circuit of  claim 2 .  
   
   
       36 . A finite impulse response filter comprising the circuit of  claim 3 .  
   
   
       37 . A finite impulse response filter comprising the circuit of  claim 4 .  
   
   
       38 . The circuit of  claim 1  further comprising a variable capacitor configured to be coupled in parallel with the gate terminal.  
   
   
       39 . The circuit  claim 2  further comprising a variable capacitor configured to be coupled in parallel with the gate terminal.  
   
   
       40 . The circuit of  claim 3  further comprising a variable capacitor configured to be coupled in parallel with the gate terminal.  
   
   
       41 . The circuit of  claim 4  further comprising a variable capacitor configured to be coupled in parallel with the gate terminal.  
   
   
       42 . The circuit of  claim 1  further comprising: 
 a further MOSFET including a further source terminal, a further drain terminal, and a further gate terminal, the further gate terminal being coupled to the gate terminal, the further source terminal configured to be coupled to a further voltage.    
   
   
       43 . The circuit of  claim 2  further comprising: 
 a further MOSFET including a further source terminal, a further drain terminal, and a further gate terminal, the further gate terminal being coupled to the gate terminal, the further source terminal configured to be coupled to a further voltage.    
   
   
       44 . The circuit of  claim 3  further comprising: 
 a further MOSFET including a further source terminal, a further drain terminal, and a further gate terminal, the further gate terminal being coupled to the gate terminal, the further source terminal configured to be coupled to a further voltage.    
   
   
       45 . The circuit of  claim 4  further comprising: 
 a further MOSFET including a further source terminal, a further drain terminal, and a further gate terminal, the further gate terminal being coupled to the gate terminal, the further source terminal configured to be coupled to a further voltage.    
   
   
       46 . A bootstrapping circuit comprising the circuit of  claim 1 .  
   
   
       47 . A bootstrapping circuit comprising the circuit of  claim 2 .  
   
   
       48 . A bootstrapping circuit comprising the circuit of  claim 3 .  
   
   
       49 . A bootstrapping circuit comprising the circuit of  claim 4 .  
   
   
       50 . A preamplifier in a comparator circuit, the preamplifier comprising the circuit of  claim 1 .  
   
   
       51 . A preamplifier in a comparator circuit, the preamplifier comprising the circuit of  claim 2 .  
   
   
       52 . A preamplifier in a comparator circuit, the preamplifier comprising the circuit of  claim 3 .  
   
   
       53 . A preamplifier in a comparator circuit, the preamplifier comprising the circuit of  claim 4.