Fast turn-on and low-capacitance SCR ESD protection

Abstract

An ESD protection device comprises a PNP and an NPN transistor having a common PN junction, first and second collector resistances, series connected at a first node, connected to a collector of the PNP transistor, third and fourth collector resistances, series connected at a second node, connected to a collector of the NPN transistor and a trigger circuit connected between the first node and the second node.

1 . An apparatus for protecting a semiconductor device from excessive charge comprising: 
 a PNP transistor and an NPN transistor formed in a semiconductive substrate, said transistors having a common PN junction;    first and second collector resistances, series connected at a first node, said first resistance also being connected to a collector of said PNP transistor;    third and fourth collector resistances, series connected at a second node, said third resistance also being connected to a collector of said NPN transistor; and    a trigger circuit connected between said first node and said second node.    
     
     
         2 . The apparatus of  claim 1  wherein the first collector resistance is formed in said semiconductive substrate.  
     
     
         3 . The apparatus of  claim 2  wherein the third collector resistance is formed in said semiconductive substrate.  
     
     
         4 . The apparatus of  claim 1  wherein said first and second collector resistances are formed in said semiconductive substrate.  
     
     
         5 . The apparatus of  claim 4  wherein said third and fourth collector resistances are formed in said semiconductive substrate.  
     
     
         6 . The apparatus of  claim 1  wherein the third collector resistance is formed in said semiconductive substrate.  
     
     
         7 . The apparatus of  claim 1  wherein the third and fourth collector resistances are formed in said semiconductive substrate.  
     
     
         8 . The apparatus of  claim 1  wherein the trigger circuit comprises a plurality of diodes connected in series between the first node and the second node.  
     
     
         9 . The apparatus of  claim 1  wherein the trigger circuit comprises a grounded gate NMOS device connected between the first node and the second node.  
     
     
         10 . The apparatus of  claim 1  wherein the trigger circuit comprises an NMOS transistor having a source and drain connected between the first node and the second node, an inverter connected to the gate of the NMOS transistor, and an input to the inverter connected to a node between a resistor and a capacitor that are connected in series between an emitter of the PNP transistor and an emitter of the NPN transistor.  
     
     
         11 . The apparatus of  claim 1  further comprising a diode connected between an emitter of the PNP transistor and an emitter of the NPN transistor.  
     
     
         12 . The apparatus of  claim 1  further comprising a guardring surrounding the apparatus.  
     
     
         13 . An apparatus for protecting a semiconductor device from excessive charge comprising: 
 a substrate having a first conductivity type;    a well region formed in said substrate, said well region having a second conductivity type opposite to said first conductivity type;    a first ohmic contact to said substrate;    a second ohmic contact to said well region;    a first diffusion region in said substrate having the second conductivity type;    a second diffusion region in said well region having the first conductivity type;    a first resistor connected between said first ohmic contact and said first diffusion region;    a second resistor connected between said second ohmic contact and said second diffusion region; and    a trigger circuit connected between the first ohmic contact and the second ohmic contact.    
     
     
         14 . The apparatus of  claim 13  wherein the first conductivity type is P and the second conductivity type is N.  
     
     
         15 . The apparatus of  claim 14  wherein the first diffusion region, the substrate and the well region form an NPN transistor.  
     
     
         16 . The apparatus of  claim 15  wherein the second diffusion region, the well region and the substrate form a PNP transistor that shares a PN junction with the NPN bipolar transistor.  
     
     
         17 . The apparatus of  claim 14  wherein the second diffusion region, the well region and the substrate form a PNP transistor.  
     
     
         18 . The apparatus of  claim 13  wherein the first resistor is formed in the substrate.  
     
     
         19 . The apparatus of  claim 13  wherein the second resistor is formed in the well region.  
     
     
         20 . The apparatus of  claim 13  wherein the trigger circuit comprises a plurability of diodes connected in series between the first ohmic contact and the second ohmic contact.  
     
     
         21 . The apparatus of  claim 13  wherein the trigger circuit comprises a grounded gate NMOS device connected between the first ohmic contact and the second ohmic contact.  
     
     
         22 . The apparatus of  claim 13  wherein the trigger circuit comprises an NMOS transistor having a source and drain connected between the first ohmic contact and the second ohmic contact, an inverter connected to the gate of the NMOS transistor, and an input to the inverter connected to a node between a resistor and a capacitor that are connected in series between the first diffusion region and the second diffusion region.  
     
     
         23 . The apparatus of  claim 13  further comprising a diode connected between the first diffusion region and the second diffusion region.  
     
     
         24 . The apparatus of  claim 13  further comprising a guardring surrounding the apparatus.  
     
     
         25 . An apparatus for protecting a semiconductor device from excessive charge comprising: 
 a substrate having a first conductivity type;    a well region formed in said substrate, said well region having a second conductivity type opposite to said first conductivity type;    a first ohmic contact to said substrate;    a second ohmic contact to said well region;    a third ohmic contact to said well region;    in said substrate, a first diffusion region having the second conductivity type;    in said well region, a second diffusion region having the first conductivity type;    a first resistor connected between said first ohmic contact and said first diffusion region; and    a trigger circuit connected between the first ohmic contact and the second ohmic contact.    
     
     
         26 . An apparatus for protecting a semiconductor device from excessive charge comprising: 
 a substrate having a first conductivity type;    a well region formed in said substrate, said well region having a second conductivity type opposite to said first conductivity type;    a first ohmic contact to said substrate;    a second ohmic contact to said well region;    a third ohmic contact to said substrate;    in said substrate, a first diffusion region having the second conductivity type;    in said well region, a second diffusion region having the first conductivity type;    a first resistor connected between said second ohmic contact and said second diffusion region; and    a trigger circuit connected between the first ohmic contact and the second ohmic contact.    
     
     
         27 . A method of protecting a semiconductor device from excessive charge comprising: 
 forming in a substrate having a first conductivity type a well region having a second conductivity type opposite to said first conductivity type;    forming a first ohmic contact to said substrate;    forming a second ohmic contact to said well region;    forming in said substrate a first diffusion region having the second conductivity type;    forming in said well region a second diffusion region having the first conductivity type;    wherein the first diffusion region, the substrate and the well region form a first bipolar transistor and the second diffusion region, the well region and the substrate form a second bipolar transistor;    connecting a first resistor between said first ohmic contact and said first diffusion region    connecting a second resistor between said second ohmic contact and said second diffusion region; and    connecting a trigger circuit between the first ohmic contact and the second ohmic contact, whereby when excessive charge triggers the trigger circuit current flows through the first and second resistors, thereby latching the lateral and vertical bipolar transistors into a low impedance state.    
     
     
         28 . The method of  claim 27  wherein the first conductivity type is P and the second conductivity type is N.  
     
     
         29 . The method of  claim 27  wherein the first bipolar transistor is an NPN transistor.  
     
     
         30 . The method of  claim 27  wherein the first bipolar transistor is a NPN transistor and the second bipolar transistor is a PNP transistor.  
     
     
         31 . The method of  claim 27  wherein the first resistor is formed in the substrate.  
     
     
         32 . The method of  claim 27  wherein the second resistor is formed in the well region.  
     
     
         33 . The method of  claim 27  wherein the trigger circuit comprises a plurality of diodes connected in series between the first ohmic contact and the second ohmic contact.  
     
     
         34 . The method of  claim 27  wherein the trigger circuit comprises a grounded gate NMOS device connected between the first ohmic contact and the second ohmic contact.  
     
     
         35 . The method of  claim 27  wherein the trigger circuit comprises an NMOS transistor having a source and drain connected between the first ohmic contact and the second ohmic contact, an inverter connected to the gate of the NMOS transistor, and an input to the inverter connected to a node between a resistor and a capacitor that are connected in series between the first diffusion region and the second diffusion region  
     
     
         36 . The method of  claim 27  further comprising the step of connecting a diode between the first diffusion region and the second diffusion region.