Diode with improved energy impulse rating

Abstract

An energy pulse clamping semiconductor diode includes a substrate having carriers of a first type of conductivity in a first, high concentration level (e.g. n++), a first major face and a second major face opposite to the first major face; a layer of semiconductor material having carriers of the first type of conductivity in a second concentration level lower than the first level (e.g. n+), and having an outer surface; a region formed at an outer surface having carriers of a second type of conductivity in a third concentration level (e.g. p+); at least one cell having carriers of the second type of conductivity in a fourth concentration level greater than the third concentration level (e.g. p++); a cathode electrode and an anode electrode. The diode is most preferably included in an overvoltage protection circuit including a PPTC resistor in series with the cathode electrode and thermally coupled to the diode.

1 . A semiconductor device consisting essentially of: 
 (a) a planar substrate of semiconductor material having carriers of a first type of conductivity in a first, high concentration level, a first major face and a second major face opposite to said first major face;    (b) a layer of semiconductor material being one of in or on said substrate adjacent said first major face, having carriers of said first type of conductivity in a second concentration level lower than said first level, and having an outer surface;    (c) at least one region formed at said outer surface and having carriers of a second type of conductivity in a third concentration level;    (d) at least one cell formed at said outer surface and having carriers of said second type of conductivity in a fourth concentration level greater than said third concentration level;    (e) a first electrode layer formed at said outer surface; and    (f) a second electrode layer formed at said second major face.    
     
     
         2 . The semiconductor device set forth in  claim 1  wherein said at least one region extends to a first predetermined depth into said layer and wherein said at least one cell extends to a second predetermined depth into said layer.  
     
     
         3 . The semiconductor device set forth in  claim 2  wherein said second predetermined depth is greater than said first predetermined depth.  
     
     
         4 . The semiconductor device set forth in  claim 2  wherein said second predetermined depth is less than or equal to said first predetermined depth.  
     
     
         5 . The semiconductor device set forth in  claim 1  wherein said carriers of said first type of conductivity are n-carriers and wherein said carriers of said second type of conductivity are p-carriers.  
     
     
         6 . The semiconductor device set forth in  claim 1  wherein said carriers of said first type of conductivity are p-carriers and wherein said carriers of said second type of conductivity are n-carriers.  
     
     
         7 . The semiconductor device set forth in  claim 1  wherein said device comprises a plurality of cells separated from each other by said region.  
     
     
         8 . The semiconductor device set forth in  claim 1  wherein said device comprises a plurality of cells and a plurality of regions, and wherein said plurality of cells are separated from each other by said plurality of regions.  
     
     
         9 . The semiconductor device set forth in  claim 1  wherein said layer comprises an epitaxial layer formed on said substrate.  
     
     
         10 . The semiconductor device set forth in  claim 1  wherein at least one of said electrodes of said device is electrically connected to a circuit protection element, and said device is in thermal contact with a circuit protection element.  
     
     
         11 . The semiconductor device set forth in  claim 10  wherein said circuit protection element comprises a polymeric positive temperature coefficient (PPTC) resistive element.  
     
     
         12 . The semiconductor device set forth in  claim 10  connected in reverse bias voltage arrangement within a protection circuit and operative to absorb an energy pulse having a voltage in excess of a predetermined reverse bias voltage level, convert said pulse to heat, and transfer said heat to said circuit protection element.  
     
     
         13 . The semiconductor device set forth in  claim 5  wherein said first electrode forms a cathode connection and said second electrode forms an anode connection, and further comprising a polymeric positive temperature coefficient (PPTC) resistive element electrically connected in series with said cathode connection and thermally coupled to said device by direct contact therewith.  
     
     
         14 . The semiconductor device set forth in  claim 13  comprising an overvoltage protection circuit wherein the PPTC resistive element is connected in series between a source and a load, and wherein said semiconductor device is connected in parallel across said load.  
     
     
         15 . The semiconductor device set forth in  claim 5  wherein the planar substrate is a negative carrier, n-type doping material having approximately at least 10 20  n-type dopant ions/cm 3 ; wherein the epitaxial layer is a negative carrier, n-type doping material having approximately 5×10 17  dopant ions/cm 3 ; the at least one region is a positive carrier, p-type doping material having p-type dopants in a range between 10 20  and 10 15  dopant ions/cm 3 , and the at least one cell is a positive carrier, p-type doping material having p-type dopants in a range between 5×10 21  and 10 15  dopant ions/cm 3 .  
     
     
         16 . A semiconductor device consisting essentially of: 
 (a) a planar substrate of semiconductor material having carriers of a first type of conductivity in a first predetermined concentration level, a first major face and a second major face opposite to said first major face;    (b) at least one region formed at said first major face and having carriers of a second type of conductivity in a second predetermined concentration level;    (c) at least one cell formed at said first major face and having carriers of said second type of conductivity in a second concentration level greater than said second concentration level;    (d) a first electrode layer formed at said first major face; and    (e) a second electrode layer formed at said second major face.    
     
     
         17 . The semiconductor device set forth in  claim 16  wherein said carriers of said first type of conductivity are n-carriers and wherein said carriers of said second type of conductivity are p-carriers.  
     
     
         18 . The semiconductor device set forth in  claim 16  wherein said carriers of said first type of conductivity are p-carriers and wherein said carriers of said second type of conductivity are n-carriers.  
     
     
         19 . The semiconductor device set forth in  claim 16  wherein said device comprises a plurality of cells separated from each other by said region.  
     
     
         20 . The semiconductor device set forth in  claim 16  wherein said device comprises a plurality of cells and a plurality of regions, and wherein said plurality of cells are separated from each other by said plurality of regions.  
     
     
         21 . The semiconductor device set forth in  claim 16  wherein at least one of said electrodes of said device is electrically connected to a circuit protection element, and said device is in thermal contact with a circuit protection element.  
     
     
         22 . The semiconductor device set forth in  claim 21  wherein said circuit protection element comprises a polymeric positive temperature coefficient (PPTC) resistive element.  
     
     
         23 . The semiconductor device set forth in  claim 21  connected in reverse bias voltage arrangement within a protection circuit and operative to absorb an energy pulse having a voltage in excess of a predetermined reverse bias voltage level, convert said pulse to heat, and transfer said heat to said circuit protection element.  
     
     
         24 . The semiconductor device set forth in  claim 17  wherein said first electrode forms a cathode connection and said second electrode forms an anode connection, and further comprising a polymeric positive temperature coefficient (PPTC) resistive element electrically connected in series with said cathode connection and thermally coupled to said device by direct contact therewith.  
     
     
         25 . The semiconductor device set forth in  claim 24  comprising an overvoltage protection circuit wherein the PPTC resistive element is connected in series between a source and a load, and wherein said semiconductor device is connected in parallel across said load.  
     
     
         26 . A method for making a semiconductor device comprising steps of: 
 (a) forming a planar substrate of semiconductor material having carriers of a first type of conductivity in a first, high concentration level, a first major face and a second major face opposite to said first major face;    (b) forming an epitaxial layer of semiconductor material on said first major face with carriers of said first type of conductivity in a second concentration level lower than said first level, and an outer surface;    (c) forming at least one region at said outer surface with carriers of a second type of conductivity in a third concentration level;    (d) forming at least one cell at said outer surface with carriers of said second type of conductivity in a fourth concentration level greater than said third concentration level;    (e) forming a first electrode layer at said outer surface; and    (f) forming a second electrode layer at said second major face.    
     
     
         27 . A method for making a semiconductor device comprising steps of: 
 (a) forming a planar substrate of semiconductor material having carriers of a first type of conductivity in a first predetermined concentration level, a first major face and a second major face opposite to said first major face;    (b) forming at least one region at said first major face with carriers of a second type of conductivity in a second predetermined concentration level;    (c) forming at least one cell at said first major face with carriers of said second type of conductivity in a second concentration level greater than said second concentration level;    (d) forming a first electrode layer formed at said first major face; and    (e) forming a second electrode layer formed at said second major face.