System and method to reduce noise in a substrate

Abstract

Disclosed herein is a system adapted to reduce noise in a substrate of a chip. The chip may include a substrate having a first well disposed there atop. The first well may be a deep well. A second well and a third may also be disposed within the first well. A first transistor may be disposed in the second well. A quiet voltage source may be connected to a body of the first transistor. A second transistor may be disposed in the third well. The first transistor may be a PMOS transistor and the second transistor may be an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor. A body of the first transistor may be resistively coupled to the second well.

1 . A system for reducing noise in a chip, the system comprising: 
 a substrate doped with a first dopant;    a first well doped with a second dopant, the first well disposed on top of the substrate;    a first circuit disposed in a second well; and    a second circuit disposed in a third well, wherein the second well and the third well are disposed within the first well.    
   
   
       2 . The system according to  claim 1 , wherein the first circuit comprises a first transistor, and the first transistor comprises a PMOS transistor.  
   
   
       3 . The system according to  claim 2 , further comprising a noisy voltage source coupled to a source of the first transistor.  
   
   
       4 . The system according to  claim 2 , further comprising a quiet voltage source connected to a body of the first transistor.  
   
   
       5 . The system according to  claim 2 , wherein a body of the first transistor is resistively coupled to the second well.  
   
   
       6 . The system according to  claim 1 , wherein the second circuit comprises a second transistor, and the second transistor comprises an NMOS transistor.  
   
   
       7 . The system according to  claim 6 , further comprising a noisy voltage source, wherein a body and a source of the second transistor are both coupled to the noisy voltage source.  
   
   
       8 . The system according to  claim 6 , wherein the body of the second transistor is capacitively coupled to the substrate.  
   
   
       9 . The system according to  claim 1 , wherein the first well is a deep well.  
   
   
       10 . The system according to  claim 1 , wherein the second well is doped with the second dopant.  
   
   
       11 . The system according to  claim 1 , wherein the third well is doped with the first dopant.  
   
   
       12 . A method for reducing noise in a chip, the method comprising: 
 disposing a substrate layer within the chip;    disposing a circuit layer within the chip;    shielding the substrate layer from the circuit layer by disposing a shielding layer therebetween; and    coupling the circuit layer to the shielding layer employing a first circuit.    
   
   
       13 . The method according to  claim 12 , wherein the first circuit comprises a first transistor, and the first transistor comprises a p-type transistor.  
   
   
       14 . The method according to  claim 12 , further comprising: 
 coupling a quiet voltage source to the first circuit; and    coupling a second circuit to the shielding layer.    
   
   
       15 . The method according to  claim 14 , wherein the second circuit comprises a second transistor, and the second transistor comprises an n-type transistor.  
   
   
       16 . The method according to  claim 15 , further comprising coupling a first noisy voltage source to a source of the second transistor.  
   
   
       17 . The method according to  claim 14 , further comprising: 
 disposing the second circuit within the circuit layer; and    resistively coupling the second circuit to the shielding layer.    
   
   
       18 . The method according to  claim 12 , further comprising disposing the first circuit within the circuit layer.  
   
   
       19 . The method according to  claim 12 , further comprising: 
 capacitively coupling the first circuit to the shielding layer; and    capacitively coupling the shielding layer to the substrate layer.    
   
   
       20 . The method according to  claim 12 , wherein the shielding layer comprises a deep N-well.