Concentric or nested container capacitor structure for integrated cicuits

Abstract

Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the nested container capacitors in the vicinity of two capacitor contact plugs. An outer capacitor plate is formed by etching back poly 1 to leave it substantially on the vertical edges of the hole and in contact with one of the plugs. At least one sacrificial sidewall is formed on the poly 1, and poly 2 is deposited over the sidewalls to form an inner capacitor plate in contact with the other plug. The structure is planarized, the sacrificial sidewalls are removed, a capacitor dielectric is formed, and is topped with poly 3. Additional structures such as a protective layer (to prevent poly 1 -to-poly 2 shorting) and a conductive layer (to strap the plugs to their respective poly layers) can also be used.

1 . A capacitor structure for an integrated circuit, comprising: 
 a first capacitor formed on the integrated circuit and having first and second plates, wherein the first plate of the first capacitor is in contact with a first node; and    a second capacitor nested within the first capacitor on the integrated circuit and having first and second plates, wherein the first plate of the second capacitor is in contact with a second node electrically isolated from the first node.    
   
   
       2 . The capacitor structure of  claim 1 , further comprising a common plate, wherein the common plate comprises a second plate of the first and second capacitors.  
   
   
       3 . The capacitor structure of  claim 1 , wherein each plate comprises a layer of deposited material.  
   
   
       4 . The capacitor structure of  claim 1 , wherein the layers constitute polysilicon.  
   
   
       5 . The capacitor structure of  claim 1 , wherein the first node is coupled to a source or drain region of a first access transistor, and wherein the second node is coupled to a source or drain region of a second access transistor.  
   
   
       6 . The capacitor structure of  claim 1 , wherein a common dielectric layer intervenes between the first and second plates of each capacitor.  
   
   
       7 . The capacitor structure of  claim 1 , wherein the first and second capacitors are concentric.  
   
   
       8 . The capacitor structure of  claim 1 , wherein the first plates of the first and second capacitors comprise substantially vertical portions.  
   
   
       9 . The capacitor structure of  claim 8 , wherein the substantially vertical portions of the first plate of the first capacitor are nested within the substantially vertical portions of first plate of the second capacitor.  
   
   
       10 . The capacitor structure of  claim 1 , wherein the common plate comprises substantially vertical portions.  
   
   
       11 . The capacitor structure of  claim 1 , wherein at least one of the nodes is in contact with one of the first plates via a conductive layer.  
   
   
       12 . The capacitor structure of  claim 1 , wherein at least one of the first plates comprises nested subplates.  
   
   
       13 . The capacitor structure of  claim 1 , wherein the first plates comprise substantially vertical sidewalls.  
   
   
       14 . The capacitor structure of  claim 1 , further comprising a third capacitor nested within the second capacitor on the integrated circuit and having first and second plates, wherein the first plate of the third capacitor is coupled to a third node electrically isolated from the first and second nodes.  
   
   
       15 . The capacitor structure of  claim 14 , wherein common plate comprises a second plate of the first, second, and third capacitors.  
   
   
       16 . A capacitor structure for an integrated circuit, comprising: 
 a first capacitor plate formed on the integrated circuit;    a second capacitor plate formed on the integrated circuit within the first capacitor plate; and    a third capacitor plate, wherein the third capacitor plate is proximate to the first capacitor plates to form a first capacitor, and wherein the third capacitor plate is proximate to the second capacitor plate to form a second capacitor.    
   
   
       17 . The capacitor structure of  claim 16 , wherein each plate comprises a layer of deposited material.  
   
   
       18 . The capacitor structure of  claim 16 , wherein the layers constitute polysilicon.  
   
   
       19 . The capacitor structure of  claim 16 , further comprising a first node in contact with the first capacitor plate, and a second node in contact with the second capacitor plate.  
   
   
       20 . The capacitor structure of  claim 19 , wherein the first node is coupled to a source or drain region of a first access transistor, and wherein the second node is coupled to a source or drain region of a second access transistor.  
   
   
       21 . The capacitor structure of  claim 19 , wherein at least one of the nodes is in contact with one of the first plates via a conductive layer.  
   
   
       22 . The capacitor structure of  claim 16 , wherein a common dielectric layer intervenes between the plates in the first and second capacitors.  
   
   
       23 . The capacitor structure of  claim 16 , wherein the first and second plates are concentric.  
   
   
       24 . The capacitor structure of  claim 16 , wherein the first and second plates comprise substantially vertical portions.  
   
   
       25 . The capacitor structure of  claim 24 , wherein the substantially vertical portions of the second plate are nested within the substantially vertical portions of first plate.  
   
   
       26 . The capacitor structure of  claim 16 , wherein the third plate comprises substantially vertical portions.  
   
   
       27 . The capacitor structure of  claim 16 , wherein at least one of the first or second plates comprises nested subplates.  
   
   
       28 . The capacitor structure of  claim 16 , further comprising a fourth capacitor plate formed on the integrated circuit within the second capacitor plate, and wherein the third capacitor plate is proximate to the fourth capacitor plate to form a third capacitor.  
   
   
       29 . The capacitor structure of  claim 16 , wherein the first and second plates comprise substantially vertical sidewalls.  
   
   
       30 . A capacitor structure for an integrated circuit, comprising: 
 a first bottom capacitor plate within a hole in the integrated circuit and in contact with a first contact;    a second bottom capacitor plate within the hole and nested within the first bottom capacitor plate and in contact with a second contact electrically isolated from the first contact; and    a top capacitor plate over the first and second bottom capacitors plates.    
   
   
       31 . The capacitor structure of  claim 30 , wherein each plate comprises a layer of deposited material.  
   
   
       32 . The capacitor structure of  claim 30 , wherein the layers constitute polysilicon.  
   
   
       33 . The capacitor structure of  claim 32 , wherein the first contact is coupled to a source or drain region of a first access transistor, and wherein the second contact is coupled to a source or drain region of a second access transistor.  
   
   
       34 . The capacitor structure of  claim 33 , wherein at least one of the contacts is in contact with one of the bottom plates via a conductive layer.  
   
   
       35 . The capacitor structure of  claim 30 , wherein a common dielectric layer intervenes between the top plate and each of the bottom plates.  
   
   
       36 . The capacitor structure of  claim 30 , wherein the bottom plates are concentric.  
   
   
       37 . The capacitor structure of  claim 30 , wherein the bottom plates comprise substantially vertical portions.  
   
   
       38 . The capacitor structure of  claim 37 , wherein the substantially vertical portions of first bottom capacitor plate are formed along edges of the hole.  
   
   
       39 . The capacitor structure of  claim 38 , wherein the substantially vertical portions of the second bottom capacitor plate are nested within the substantially vertical portions of first bottom capacitor plate.  
   
   
       40 . The capacitor structure of  claim 30 , wherein the top plate comprises substantially vertical portions.  
   
   
       41 . The capacitor structure of  claim 30 , wherein at least one of the bottom plates comprises nested subplates.  
   
   
       42 . The capacitor structure of  claim 30 , further comprising a third bottom capacitor plate within the hole and nested within the second bottom capacitor plate and in contact with a third contact electrically isolated from the first and second contacts, and wherein the top capacitor plate appears over the third bottom capacitor plate.  
   
   
       43 . The capacitor structure of  claim 30 , wherein the first and second plates comprise substantially vertical sidewalls.  
   
   
       44 . The capacitor structure of  claim 30 , wherein at least one of the contacts appear at partially outside of the hole.  
   
   
       45 . The capacitor structure of  claim 44 , wherein at least one of the contacts appear at completely outside of the hole.  
   
   
       46 . A dynamic random access memory, comprising: 
 a first access transistor;    a second access transistor; and    a capacitor structure formed in an area, comprising: 
 a first capacitor having first and second plates, wherein the first plate of the first capacitor is coupled to the first access transistor,  
 a second capacitor nested within the first capacitor on the integrated circuit and having first and second plates, wherein the first plate of the second capacitor is coupled to the second access transistor, and  
 a common plate, wherein the common plate comprises a second plate of the first and second capacitors.  
   
   
   
       47 . The dynamic random access memory of  claim 46 , wherein the capacitors are coupled to source or drain regions of the access transistors.  
   
   
       48 . The dynamic random access memory of  claim 47 , wherein the capacitors are coupled to source or drain regions of the access transistors through contacts.  
   
   
       49 . The dynamic random access memory of  claim 46 , wherein at least one of the contacts appear at partially outside of the area.  
   
   
       50 . The dynamic random access memory of  claim 46 , wherein at least one of the contacts appear at completely outside of the area.  
   
   
       51 . The dynamic random access memory of  claim 46 , wherein the common plate is coupled to a reference voltage.  
   
   
       52 . The dynamic random access memory of  claim 46 , wherein a common dielectric layer intervenes between the first and second plates of each capacitor.  
   
   
       53 . The dynamic random access memory of  claim 46 , wherein the first and second capacitors are concentric.  
   
   
       54 . The dynamic random access memory of  claim 46 , wherein the first plates of the first and second capacitors comprise substantially vertical portions.  
   
   
       55 . The dynamic random access memory of  claim 54 , wherein the substantially vertical portions of the first plate of the first capacitor are nested within the substantially vertical portions of first plate of the second capacitor.  
   
   
       56 . The dynamic random access memory of  claim 46 , wherein the common plate comprises substantially vertical portions.  
   
   
       57 . The dynamic random access memory of  claim 46 , wherein at least one of the nodes is in contact with one of the first plates via a conductive layer.  
   
   
       58 . The dynamic random access memory of  claim 46 , wherein at least one of the first plates comprises nested subplates.  
   
   
       59 . The dynamic random access memory of  claim 46 , wherein the first plates comprise substantially vertical sidewalls.  
   
   
       60 . A dynamic random access memory, comprising: 
 a first access transistor;    a second access transistor; and    a capacitor structure formed in an area, comprising: 
 a first capacitor plate coupled to the first access transistor,  
 a second capacitor plate within the first capacitor plate coupled to the second access transistor, and  
 a third capacitor plate, wherein the third capacitor plate is proximate to the first capacitor plates to form a first capacitor, and wherein the third capacitor plate is proximate to the second capacitor plate to form a second capacitor.  
   
   
   
       61 . The dynamic random access memory of  claim 60 , wherein the plates are coupled to source or drain regions of the access transistors.  
   
   
       62 . The dynamic random access memory of  claim 61 , wherein the plates are coupled to source or drain regions of the access transistors through contacts.  
   
   
       63 . The dynamic random access memory of  claim 60 , wherein at least one of the contacts appear at partially outside of the area.  
   
   
       64 . The dynamic random access memory of  claim 60 , wherein at least one of the contacts appear at completely outside of the area.  
   
   
       65 . The dynamic random access memory of  claim 60 , wherein the third plate is coupled to a reference voltage.  
   
   
       66 . The dynamic random access memory of  claim 60 , wherein a common dielectric layer intervenes between the plates in the first and second capacitors.  
   
   
       67 . The dynamic random access memory of  claim 60 , wherein the first and second plates are concentric.  
   
   
       68 . The dynamic random access memory of  claim 60 , wherein the first and second plates comprise substantially vertical portions.  
   
   
       69 . The dynamic random access memory of  claim 68 , wherein the substantially vertical portions of the second plate are nested within the substantially vertical portions of first plate.  
   
   
       70 . The dynamic random access memory of  claim 60 , wherein the third plate comprises substantially vertical portions.  
   
   
       71 . The dynamic random access memory of  claim 60 , wherein at least one of the first or second plates comprises nested subplates.  
   
   
       72 . The dynamic random access memory of  claim 60 , further comprising a fourth capacitor plate formed on the integrated circuit within the second capacitor plate, and wherein the third capacitor plate is proximate to the fourth capacitor plate to form a third capacitor.  
   
   
       73 . The dynamic random access memory of  claim 60 , wherein the first and second plates comprise substantially vertical sidewalls.  
   
   
       74 . A method for forming a capacitor structure for an integrated circuit, comprising: 
 forming a hole in a dielectric layer on the integrated circuit to define a capacitor area;    forming a first bottom capacitor plate within the hole in the integrated circuit and in contact with a first contact;    forming a second bottom capacitor plate within the hole and nested within the first bottom capacitor plate and in contact with a second contact electrically isolated from the first contact; and    forming a top capacitor plate over the first and second bottom capacitors plates.    
   
   
       75 . The method of  claim 74 , wherein forming the hole exposes at least one of the first or second contacts.  
   
   
       76 . The method of  claim 74 , wherein the first bottom plate is formed as a sidewall on edges of the hole by etch back processing.  
   
   
       77 . The method of  claim 76 , further comprising forming at least one sidewall on first bottom plate sidewalls.  
   
   
       78 . The method of  claim 77 , wherein the second bottom plate is formed on the at least one sidewall.  
   
   
       79 . The method of  claim 78 , further comprising planarizing the second bottom plate to expose the surface of the dielectric.  
   
   
       80 . The method of  claim 79 , further comprising removing the at least one sidewall after planarization.  
   
   
       81 . The method of  claim 80 , wherein the at least one sidewall is removed by liquid etching.  
   
   
       82 . The method of  claim 74 , wherein a capacitor dielectric is formed on the bottom plates prior to formation of the top plate.  
   
   
       83 . The method of  claim 74 , wherein the dielectric layer overlies the contacts.  
   
   
       84 . The method of  claim 83 , further comprising forming a conductive layer over at least one of the contacts prior to dielectric formation.  
   
   
       85 . The method of  claim 84 , wherein one of the bottom plates is brought in contact with a contact via the conductive layer over that contact.  
   
   
       86 . The method of  claim 74 , wherein at least one of the contacts is outside the area.  
   
   
       87 . The method of  claim 74 , further comprising forming a protective layer over at least one of the contacts prior to dielectric formation.  
   
   
       88 . The method of  claim 87 , further comprising removing at least a portion of the protective later over the contact, and wherein that contact is in contact with the second bottom plate.  
   
   
       89 . A method for forming a capacitor structure for an integrated circuit, comprising: 
 forming a first capacitor on the integrated circuit having first and second plates, wherein the first plate of the first capacitor is in contact with a first node; and    forming a second capacitor nested within the first capacitor on the integrated circuit having first and second plates, wherein the first plate of the second capacitor is in contact with a second node electrically isolated from the first node.    
   
   
       90 . The method of  claim 89 , further comprising forming a common plate, wherein the common plate comprises a second plate of the first and second capacitors.  
   
   
       91 . The method of  claim 89 , wherein each plate comprises a layer of deposited material.  
   
   
       92 . The method of  claim 89 , wherein the layers constitute polysilicon.  
   
   
       93 . The method of  claim 89 , wherein the first node is coupled to a source or drain region of a first access transistor, and wherein the second node is coupled to a source or drain region of a second access transistor.  
   
   
       94 . The method of  claim 89 , wherein a common dielectric layer intervenes between the first and second plates of each capacitor.  
   
   
       95 . The method of  claim 89 , wherein the first and second capacitors are concentric.  
   
   
       96 . The method of  claim 89 , wherein the first plates of the first and second capacitors comprise substantially vertical portions.  
   
   
       97 . The method of  claim 96 , wherein the substantially vertical portions of the first plate of the first capacitor are nested within the substantially vertical portions of first plate of the second capacitor.  
   
   
       98 . The method of  claim 89 , wherein the common plate comprises substantially vertical portions.  
   
   
       99 . The method of  claim 89 , wherein at least one of the nodes is in contact with one of the first plates via a conductive layer.  
   
   
       100 . The method of  claim 89 , wherein at least one of the first plates comprises nested subplates.  
   
   
       101 . The method of  claim 89 , wherein the first plates comprise substantially vertical sidewalls.  
   
   
       102 . The method of  claim 89 , further comprising a third capacitor nested within the second capacitor on the integrated circuit and having first and second plates, wherein the first plate of the third capacitor is coupled to a third node electrically isolated from the first and second nodes.  
   
   
       103 . The method of  claim 102 , wherein common plate comprises a second plate of the first, second, and third capacitors.