Flash memory cell and manufacturing method thereof

Abstract

A flash memory cell includes a first conductive type substrate, a stacked gate structure, a first conductive type source/drain region, a metal silicide layer, an inter-layer dielectric layer and a contact plug. The first conductive type substrate has a second conductive type shallow well already formed thereon. The metal silicide layer is disposed within the first conductive type drain region. The contact plug is disposed within the inter-layer dielectric layer and electrically connected with the metal silicide layer in the first conductive type drain region to reduce resistance between the contact plug, the first conductive type drain region and the second conductive type shallow well and increase read-out speed of the flash memory.

1 . A method of fabricating a flash memory cell, comprising the steps of: 
 providing a first conductive type substrate;    forming a second conductive type shallow well in the first conductive type substrate;    forming a stacked gate structure over the first conductive type substrate, wherein the stacked gate structure comprises a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially stacked over the first conductive type substrate and the stacked gate structure is disposed over the second conductive type shallow well;    forming a first conductive type source region and a first conductive type drain region in the first conductive type substrate within the second conductive type shallow well on each side of the stacked gate structure;    forming a metal silicide layer within the first conductive type drain region such that the metal silicide layer passes through the junction between the first conductive type drain region and the second conductive type shallow well;    forming an inter-layer dielectric layer over the first conductive type substrate and the stacked gate structure; and    forming a contact plug in the inter-layer dielectric layer such that the contact plug is electrically connected to the first conductive type drain region and the second conductive type shallow well through the metal silicide layer.    
   
   
       2 . The method of  claim 1 , wherein after forming the first conductive type source region and the first conductive type drain region but before forming the inter-layer dielectric layer, further comprises forming spacers on the sidewalls of the stacked gate structure.  
   
   
       3 . The method of  claim 1 , wherein the step of forming the metal silicide layer within the first conductive type drain region further comprises forming the metal silicide layer over the control gate of the stacked gate structure.  
   
   
       4 . The method of  claim 1 , wherein the first conductive type is n-type and the second conductive type is p-type.  
   
   
       5 . A method of fabricating a flash memory cell, comprising the steps of: 
 providing a first conductive type substrate;    forming a second conductive type shallow well in the first conductive type substrate;    forming a stacked gate structure over the first conductive type substrate, wherein the stacked gate structure comprises a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially stacked over the first conductive type substrate and the stacked gate structure is disposed over the second conductive type shallow well;    forming a first conductive type source region and a first conductive type drain region in the first conductive type substrate within the second conductive type shallow well on each side of the stacked gate structure;    forming a metal silicide layer within the first conductive type drain region;    forming a doped region underneath the metal silicide layer such that the doped region connects electrically with the metal silicide layer and passes through the junction between the first conductive type drain region and the second conductive type shallow well;    forming an inter-layer dielectric layer over the first conductive type substrate and the stacked gate structure, wherein the inter-layer dielectric layer has an opening that exposes a portion of the first conductive type drain region; and    forming a contact plug inside the opening of the inter-layer dielectric layer such that the contact plug is electrically connected to the first conductive type drain and the second conductive type shallow well through the metal silicide layer and the doped region.    
   
   
       6 . The method of  claim 5 , wherein after forming the metal silicide layer but before forming the inter-layer dielectric layer, further comprises: 
 forming a patterned photoresist layer over the stacked gate structure and the first conductive type substrate to expose the metal silicide layer;    forming the doped region using the patterned photoresist layer as a mask; and    removing the patterned photoresist layer.    
   
   
       7 . The method of  claim 5 , wherein the step of forming the doped region comprises performing an ion implantation.  
   
   
       8 . The method of  claim 5 , wherein the step of forming the metal silicide layer within the first conductive type drain region further comprises forming the metal silicide layer over the control gate of the stacked gate structure.  
   
   
       9 . The method of  claim 5 , wherein the first conductive type is n-type and the second conductive type is p-type.  
   
   
       10 . A method of fabricating a flash memory cell, comprising the steps of: 
 providing a first conductive type substrate;    forming a second conductive type shallow well in the first conductive type substrate;    forming a stacked gate structure over the first conductive type substrate, wherein the stacked gate structure comprises a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially stacked over the first conductive type substrate and the stacked gate structure is disposed over the second conductive type shallow well;    forming a first conductive type source region and a first conductive type drain region in the first conductive type substrate within the second conductive type shallow well on each side of the stacked gate structure;    forming a doped region within the first conductive type drain region such that the doped region passes through the junction between the first conductive type drain region and the second conductive type shallow well;    forming a metal silicide layer within the first conductive type drain region such that the metal silicide layer is electrically connected to the doped region;    forming an inter-layer dielectric layer over the first conductive type substrate and the stacked gate structure, wherein the inter-layer dielectric layer has an opening that exposes a portion of the first conductive type drain region; and    forming a contact plug inside the opening of the inter-layer dielectric layer such that the contact plug is electrically connected to the metal silicide layer.    
   
   
       11 . The method of  claim 10 , wherein after forming the first conductive type source region and the first conductive type drain region but before forming the metal silicide layer, further comprises forming spacers on the sidewalls of the stacked gate structure such that the metal silicide layer is disposed over the exposed portion of the first conductive type drain region between the spacers.  
   
   
       12 . The method of  claim 10 , wherein the step of forming the metal silicide layer within the first conductive type drain region further comprises forming the metal silicide layer over the control gate of the stacked gate structure.  
   
   
       13 . The method of  claim 10 , wherein the step of forming the doped region comprises: 
 forming a patterned photoresist layer over the first conductive type substrate and the stacked gate structure to expose a portion of the first conductive type drain region;    forming the doped region in the first conductive type drain region and its underlying second conductive type shallow well exposed by the patterned photoresist layer; and    removing the patterned photoresist layer.    
   
   
       14 . The method of  claim 10 , wherein the step of forming the doped region comprises performing an ion implantation.  
   
   
       15 . The method of  claim 10 , wherein the first conductive type is n-type and the second conductive type is p-type.  
   
   
       16 . A flash memory cell, comprising: 
 a first conductive type substrate having a second conductive type shallow well already formed therein;    a stacked gate structure disposed over the first conductive type substrate, wherein the stacked gate structure comprises a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially stacked over the first conductive type substrate;    a first conductive type source region disposed in the first conductive type substrate within the second conductive type shallow well on one side of the stacked gate structure;    a first conductive type drain region disposed in the first conductive type substrate within the second conductive type shallow well on the other side of the stacked gate structure;    a metal silicide layer disposed within the first conductive type drain region such that the metal silicide layer passes through the junction between the first conductive type drain region and the second conductive type shallow well;    an inter-layer dielectric layer disposed over the first conductive type substrate and the stacked gate; and    a contact plug formed in the inter-layer dielectric layer such that the contact plug is electrically connected to the first conductive type drain region and the second conductive type shallow well through the metal silicide layer.    
   
   
       17 . The flash memory cell of  claim 16 , wherein the flash memory cell further comprises spacers disposed on the sidewalls of the stacked gate structure such that the metal silicide layer is disposed within the first conductive type drain region exposed by the spacers.  
   
   
       18 . The flash memory cell of  claim 16 , wherein the flash memory cell further comprises a cap layer disposed over the control gate of the stacked gate structure.  
   
   
       19 . The flash memory cell of  claim 16 , wherein the first conductive type is an n-type and the second conductive type is a p-type.  
   
   
       20 . A flash memory cell, comprising: 
 a first conductive type substrate having a second conductive type shallow well already formed therein;    a stacked gate structure disposed over the first conductive type substrate, wherein the stacked gate structure comprises a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate sequentially stacked over the first conductive type substrate;    a first conductive type source region disposed in the first conductive type substrate within the second conductive type shallow well on one side of the stacked gate structure;    a first conductive type drain region disposed in the first conductive type substrate within the second conductive type shallow well on the other side of the stacked gate structure;    a metal silicide layer disposed within the first conductive type drain region;    a doped region disposed within the first conductive type drain region and the second conductive type shallow well underneath the metal silicide layer such that the first conductive type drain region and the second conductive type shallow well are electrically shorted together through the doped region;    an inter-layer dielectric layer disposed over the first conductive type substrate and the stacked gate; and    a contact plug formed in the inter-layer dielectric layer such that the contact plug is electrically connected to the first conductive type drain region and the second conductive type shallow well through the metal silicide layer and the doped region.    
   
   
       21 . The flash memory cell of  claim 20 , wherein the flash memory cell further comprises spacers disposed on the sidewalls of the stacked gate structure such that the metal silicide layer is disposed within the first conductive type drain region exposed by the spacers.  
   
   
       22 . The flash memory cell of  claim 20 , wherein the flash memory cell further comprises a cap layer disposed over the control gate of the stacked gate structure.  
   
   
       23 . The flash memory cell of  claim 20 , wherein the first conductive type is n-type and the second conductive type is p-type.