Data processing system and data processing method

Abstract

A data processing system ( 1 ) has an erasable and programmable non-volatile memory ( 5 ) and a central processing unit ( 2 ). The central processing unit allows only a specified partial storage area ( 20 Ba) of the non-volatile memory to be intended for a software ECC process. Since ECC codes are added to the partial storage area alone and an error correction is made thereto to thereby increase the number of rewrite assurances, substantially needless waste of each storage area by ECC codes can b avoided as compared with a configuration in which the ECC codes are added to all the write data without distinction regardless of the storage areas. Further, since software copes with ECC processing, ECC correcting capability matched with a device characteristic of the non-volatile memory can easily be selected.

1 - 34 . (canceled)  
   
   
       35 . A data processing device comprising a nonvolatile memory and a central processing unit, 
 wherein said central processing unit controls a first programming operation for storing data to said nonvolatile memory and controls a second programming operation for storing data to said nonvolatile memory,    wherein in said first programming operation, said central processing unit writes first data with an error correct code for said first data to a first area of said nonvolatile memory,    wherein in said second programming operation, said central processing unit writes second data without an error correct code for said second data to a second area of said nonvolatile memory.    
   
   
       36 . A data processing device according to  claim 35 , 
 wherein said second data includes a program executed by said central processing unit, and    wherein said first data includes a parameter data used for executing said program.    
   
   
       37 . A data processing device according to  claim 36 , 
 wherein said nonvolatile memory stores an error correcting program for error correcting to said first data.    
   
   
       38 . A data processing device according to  claim 37 , 
 wherein said central processing unit generates said error correct code for said first data in response to performing said first programming operation.    
   
   
       39 . A data processing device according to  claim 38 , 
 wherein said nonvolatile memory has a plurality of nonvolatile memory cells, each of which is capable of storing a two or more bits.