Semiconductor wafer and manufacturing process thereof

Abstract

A semiconductor wafer includes a wafer body, a plurality of analog IC dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two dies wherein each of the dies has an internal circuit formed therewithin and at least a terminal pad formed along the scribe line, and a conductive arrangement including at least a conductive element formed on the wafer body to electrically connect the terminal pad with the internal circuit of the die in such a manner that when the die is cut off from the wafer body along the scribe line, the terminal pad is cut off from the die so as to keep the internal circuit in the die.

1 . A process of manufacturing a semiconductor wafer, comprising the steps of: 
 (a) spacedly and alignedly forming a plurality of analog IC dies on a wafer body to define a scribe line as a margin formed between each two said dies, wherein each of said dies has an internal circuit formed therewithin and at least a terminal pad;    (b) aligning said terminal pad on said scribe line of said wafer body adjacent to said respective die;    (c) forming a conductive element on said wafer body to electrically connect said terminal pad with said internal circuit of said die; and    (d) cutting off said die from said wafer body along said scribe line thereof such that said terminal pad is removed from said die so as to keep said internal circuit within said die.    
   
   
       2 . The process, as recited in  claim 1 , wherein said terminal pad, having a comb shaped, defines a plurality of terminal teeth spacedly formed on said scribe line of said wafer body for preventing a residue of said terminal pad stayed at a cutting tip of a cutting tool when said die is cut off from said wafer body, wherein said conductive element is extended from said scribe line of said wafer body to said die so as to electrically connect said terminal teeth of said terminal pad with said internal circuit of said die.  
   
   
       3 . The process, as recited in  claim 1 , wherein said terminal pad is embodied as a trim pad formed on said scribe line of said wafer body, wherein each of said dies further has a trim fuse disposed therewithin to electrically connect with said trim pad of said terminal pad, such that said die is trimmed before said die is cut off from said wafer body.  
   
   
       4 . The process, as recited in  claim 2 , wherein said terminal pad is embodied as a trim pad formed on said scribe line of said wafer body, wherein each of said dies further has a trim fuse disposed therewithin to electrically connect with said trim pad of said terminal pad, such that said die is trimmed before said die is cut off from said wafer body.  
   
   
       5 . The process, as recited in  claim 1 , wherein said terminal pad is embodied as a test pad formed on said scribe line of said wafer body, wherein said conductive element is extended from said scribe line of said wafer body to said die so as to electrically connect said test pad of said terminal pad with said internal circuit of said die such that said die is tested before said die is cut off from said wafer body.  
   
   
       6 . The process, as recited in  claim 2 , wherein said terminal pad is embodied as a test pad formed on said scribe line of said wafer body, wherein said conductive element is extended from said scribe line of said wafer body to said die so as to electrically connect said test pad of said terminal pad with said internal circuit of said die such that said die is tested before said die is cut off from said wafer body.  
   
   
       7 . A semiconductor wafer, as recited in  claim 1 , wherein said conductive element is made of metal layer.  
   
   
       8 . A semiconductor wafer, as recited in  claim 2 , wherein said conductive element is made of metal layer.  
   
   
       9 . A semiconductor wafer, as recited in  claim 4 , wherein said conductive element is made of metal layer.  
   
   
       10 . A semiconductor wafer, as recited in  claim 1 , wherein said conductive element is made of poly layer.  
   
   
       11 . A semiconductor wafer, as recited in  claim 2 , wherein said conductive element is made of poly layer.  
   
   
       12 . A semiconductor wafer, as recited in  claim 4 , wherein said conductive element is made of poly layer.