Semiconductor-on-insulating (SOI) field effect transistors with body contacts and methods of forming same

Abstract

Semiconductor-on-insulator (SOI) field effect transistors include a semiconductor substrate and a first semiconductor active region on a first portion of a surface of the substrate. A first electrically insulating layer is provided. This first electrically insulating layer extends on a second portion of the surface of the substrate and also on a first sidewall of the first semiconductor active region. A second electrically insulating layer is provided, which extends on a third portion of the surface of the semiconductor substrate. The second electrically insulating layer also extends on a second sidewall of the first semiconductor active region. A second semiconductor active region is provided on the first semiconductor active region. The second semiconductor active region extends on the first semiconductor active region and on ends of the first and second electrically insulating layers. Source and drain regions are also provided, which are electrically coupled to opposite ends of the second semiconductor active region. An insulated gate electrode extends on the second semiconductor active region and opposite the first semiconductor active region.

1 . A semiconductor-on-insulator (SOI) field effect transistor with body contact, comprising: 
 a semiconductor substrate;    a first semiconductor active region on a first portion of a surface of said semiconductor substrate;    a first electrically insulating layer extending on a second portion of the surface of said semiconductor substrate and a first sidewall of said first semiconductor active region;    a second electrically insulating layer extending on a third portion of the surface of said semiconductor substrate and a second sidewall of said first semiconductor active region;    a second semiconductor active region extending on said first semiconductor active region and on ends of said first and second electrically insulating layers;    source and drain regions electrically coupled to opposite ends of said second semiconductor active region; and    an insulated gate electrode extending on said second semiconductor active region and opposite said first semiconductor active region.    
   
   
       2 . The transistor of  claim 1 , wherein the first and second electrically insulating layers having L-shaped cross-sections when viewed in transverse cross-section.  
   
   
       3 . The transistor of  claim 1 , wherein said first and second semiconductor active regions and said source and drain regions comprise epitaxially grown silicon.  
   
   
       4 . A semiconductor device comprising: 
 a silicon substrate;    a first silicon layer divided into two portions on the silicon substrate;    an insulator pattern having a portion interposed between the first silicon layer and the silicon substrate that is parallel to the upper surface of the silicon substrate and a portion formed on a portion of the sidewalls of the first silicon layer that is perpendicular to the upper surface of the silicon substrate such that the insulator pattern is symmetrical;    a second silicon layer formed on the silicon substrate and surrounded by the insulator pattern, wherein an upper surface of the second silicon layer lies in the same plane as an upper surface of the insulator pattern;    a third silicon layer formed on the second silicon layer, wherein an upper surface of the third silicon layer lies in the same plane as the upper surface of the first silicon layer;    a gate insulator layer and a gate electrode formed with equal widths on the third silicon layer; and    a spacer formed on the sidewalls of the gate insulator and the gate electrode, wherein a source region and a drain region, each having an extension unit, exist in the third silicon layer below the spacer, and on the first silicon layer.    
   
   
       5 . The semiconductor device of  claim 4 , wherein the source region and the drain region are insulated from the silicon substrate by the portion of the insulator pattern parallel to the upper surface of the silicon substrate, and the extension unit is insulated from the silicon substrate by the portion of the insulator pattern perpendicular to the upper surface of the silicon substrate.  
   
   
       6 . The semiconductor device of  claim 4 , wherein the sidewalls of the first silicon layer and the sidewalls of the spacer are arranged to be perpendicular to the upper surface of the silicon substrate.  
   
   
       7 . The semiconductor device of  claim 6 , wherein an interface between the spacer and the gate electrode is flat.  
   
   
       8 . The semiconductor device of  claim 6 , wherein the spacer has a convex surface that faces the gate electrode, and the gate electrode has a concave surface that faces the spacer.  
   
   
       9 . The semiconductor device of  claim 4 , wherein junction depths of the source region and the drain region are equal to a thickness of the first silicon layer.  
   
   
       10 . The semiconductor device of  claim 4 , wherein the first, second, and third silicon layers have an epitaxial relation with the silicon substrate.  
   
   
       11 . A method of forming a semiconductor-on-insulator (SOI) field effect transistor with body contact, comprising: 
 forming a semiconductor substrate comprising a bulk semiconductor region, a sacrificial layer on the bulk semiconductor region and a semiconductor source/drain layer on the sacrificial layer;    selectively etching through the semiconductor source/drain layer to define an opening therein and expose a portion of the sacrificial layer;    selectively etching back a portion of the sacrificial layer to expose an underside surface of the semiconductor source/drain layer and define a gap between the semiconductor source/drain layer and the bulk semiconductor region;    filling the gap and lining sidewalls of the opening in the semiconductor source/drain layer with an electrically insulating layer;    selectively etching a portion of the electrically insulating layer in the opening to expose a portion of the bulk semiconductor region;    epitaxially growing a first semiconductor active region from the exposed portion of the bulk semiconductor region; then    selectively etching back the electrically insulating layer from within the opening in the semiconductor source/drain layer to expose sidewall portions of the semiconductor source/drain layer;    epitaxially growing a second semiconductor active region that extends on the first semiconductor active region and on the exposed sidewall portions of the semiconductor source/drain layer; and    forming an insulated gate electrode on the second semiconductor active region.    
   
   
       12 . The method of  claim 11 , wherein the sacrificial layer is selected from the group consisting of SiGe and CaF 2 .  
   
   
       13 . The method of  claim 11 , wherein said step of selectively etching through the semiconductor source/drain layer comprises forming an etching mask having an opening therein on the semiconductor source/drain layer; and wherein said step of forming an insulated gate electrode comprises forming a gate electrode spacer layer on the etching mask, selectively etching back a portion of the gate electrode spacer layer to expose a portion of the second semiconductor active region, and thermally oxidizing the exposed portion of the second semiconductor active region to define a gate insulating layer.  
   
   
       14 . The method of  claim 13 , wherein said step of thermally oxidizing the exposed portion of the second semiconductor active region is followed by the steps of: 
 forming a gate electrode layer that extends on the gate insulating layer and on an upper surface of the etching mask;    planarizing the gate electrode layer to define a gate electrode in the opening in the etching mask and expose the upper surface of the etching mask;    etching back a portion of the etching mask to expose portions of the semiconductor source/drain layer; and    implanting source/drain region dopants into the exposed portions of the semiconductor source/drain layer.    
   
   
       15 . A method of manufacturing a semiconductor device, the method comprising: 
 forming sequentially a sacrificial layer and a first silicon layer on a silicon substrate by epitaxial growth;    forming a mask nitride layer on the first silicon layer to expose a region where a gate is to be formed;    etching the first silicon layer to form a groove exposing the sacrificial layer using the mask nitride layer as an etch mask;    removing the sacrificial layer selectively with respect to the first silicon layer and the silicon substrate;    depositing an insulator to fill a space from which the sacrificial layer has been removed, and to cover an inner wall of the groove and an upper surface of the mask nitride layer;    forming an insulator pattern exposing the upper surface of the mask nitride layer and an upper surface of a portion of the silicon substrate exposed by the groove by etching the insulator;    forming a second silicon layer by epitaxially growing silicon on the portion of the silicon substrate exposed by the groove, the second silicon layer being lower than the mask nitride layer;    etching the insulator pattern such that make an upper surface of the insulator pattern lies in the same plane as an upper surface of the second silicon layer within the groove;    forming a third silicon layer by epitaxially growing silicon on the second silicon layer such that an upper surface of the third silicon layer lies in the same plane as a lower surface of the mask nitride layer within the groove;    forming a spacer exposing the third silicon layer on the inner wall of the groove;    forming a gate insulator on the third silicon layer;    filling the groove with a gate conductive layer and then planarizing the gate conductive layer to form a buried gate electrode in the mask nitride layer; and    forming a source region and a drain region, each having an extension unit over the insulator pattern, by removing the nitride layer to expose the first silicon layer, and then ion implanting the exposed first silicon layer.    
   
   
       16 . The method of  claim 15 , wherein the sacrificial layer has an etch selectivity with respect to silicon and has a lattice constant similar to the lattice constant of silicon.  
   
   
       17 . The method of  claim 16 , wherein the sacrificial layer is composed of SiGe or CaF 2 .  
   
   
       18 . The method of  claim 17 , wherein the sacrificial layer is composed of SiGe, and is wet-etched using a solution mixture of nitride acid, acetic acid, and hydrofluoric acid when being removed.  
   
   
       19 . The method of  claim 15 , wherein junction depths of the source region and the drain region are equal to a thickness of the first silicon layer.  
   
   
       20 . The method of  claim 15 , further comprising a mask oxide layer on the first silicon layer before the forming of the mask nitride layer.  
   
   
       21 . The method of  claim 15 , wherein the insulator is composed of HfSiO 2 , HfO 2 , or silicon oxide.  
   
   
       22 . The method of  claim 15 , wherein the insulator pattern is formed by anisotropic blanket etching.  
   
   
       23 . The method of  claim 15 , wherein the forming of the insulator pattern comprising: 
 chemical mechanical polishing (CMP) the insulator to expose the upper surface of the mask nitride layer; and    anisotropically blanket etching the insulator to expose the upper surface of the portion of the silicon substrate at the bottom of the groove.    
   
   
       24 . The method of  claim 15 , wherein the insulator pattern includes a portion interposed between the first silicon layer and the silicon substrate that is parallel to the upper surface of the silicon substrate, and a portion disposed on the inner walls of the groove that is perpendicular to the upper surface of the silicon substrate.  
   
   
       25 . The method of  claim 24 , wherein the source region and the drain region are insulated from the silicon substrate by the portion of the insulator pattern parallel to the upper surface of the silicon substrate, and the extension unit is insulated from the silicon substrate by the portion of the insulator pattern perpendicular to the upper surface of the silicon substrate.  
   
   
       26 . The method of  claim 15 , wherein the insulator pattern is formed by isotropic etching.  
   
   
       27 . The method of  claim 15 , wherein the upper surface of the second silicon layer is a depth of the extension unit of the source region and the drain region insulated from the silicon substrate.  
   
   
       28 . The method of  claim 15 , wherein the forming of the spacer comprises 
 depositing a silicon oxide layer that does not fill the groove; and    isotropically blanket etching the silicon oxide layer.    
   
   
       29 . The method of  claim 28 , further comprising controlling the width of the gate electrode embedded in the mask nitride layer by controlling the thickness of the silicon oxide layer.  
   
   
       30 . The method of  claim 15 , further comprising performing local channel ion implantation (LCI) on the third silicon layer using the mask nitride layer and the spacer as an ion implantation mask.  
   
   
       31 . The method of  claim 15 , wherein the gate conductive layer is composed of doped polysilicon or metal.  
   
   
       32 . The method of  claim 15 , wherein the second silicon layer and the insulator pattern have the same thickness.  
   
   
       33 . The method of  claim 32 , wherein the forming of the source region and the drain region comprises: 
 exposing the first silicon layer by removing the mask nitride layer;    forming a fourth silicon layer on the first silicon layer by epitaxial growth; and    elevating the source region and the drain region by ion-implanting the first and fourth silicon layers.    
   
   
       34 . The method of  claim 15 , wherein the spacer has a rounded upper edge.  
   
   
       35 . The method of  claim 32 , wherein the spacer has a rounded upper edge.