Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry

Abstract

Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. Preferably, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors. In another embodiment, a plurality of shallow trench isolation regions are formed within a substrate and define a plurality of active areas having widths at least some of which being no greater than about one micron (or less), with some of the widths preferably being different. One or more gate lines may be coupled to the respective active areas to provide individual transistors, with the transistors corresponding to the active areas having the different widths having different threshold voltages. In another embodiment, two field effect transistors are fabricated having different threshold voltages without using a separate channel implant for one of the transistors versus the other.

1 - 50 . (canceled)  
   
   
       51 . A method of forming integrated circuitry, comprising: 
 forming a plurality of spaced isolation regions in a substrate, the space between each pair of isolation regions comprising an active area width within the substrate, at least two active area widths being formed and comprising different active area widths; and    fabricating a field effect transistor within each of the at least two active area widths, the field effect transistors comprising different threshold voltages which correspond to the different respective active area widths.    
   
   
       52 . The method of  claim 51 , wherein the fabricating comprises forming at least one of the field effect transistors to have an active area width of less than one micron.  
   
   
       53 . The method of  claim 51 , wherein the fabricating comprises forming the field effect transistors to have respective active area widths of less than one micron.  
   
   
       54 . The method of  claim 51 , wherein the fabricating comprises fabricating using at least one common channel implant for the field effect transistors.  
   
   
       55 . The method of  claim 51 , wherein the fabricating comprises fabricating using more than one common channel implant for the field effect transistors.  
   
   
       56 . The method of  claim 51 , wherein the fabricating comprises fabricating using at least one common channel implant for the field effect transistors, and the at least one common channel implant comprises the only implant which defines the threshold voltage for the field effect transistors.  
   
   
       57 . The method of  claim 51 , wherein the field effect transistors comprise the same conductivity type.  
   
   
       58 . The method of  claim 51 , wherein the substrate comprises the same conductivity type.