Thin film transistor (TFT) and flat panel display including the TFT and their methods of manufacture

Abstract

A Thin Film Transistor (TFT) reduces interconnection resistance of source/drain electrodes, prevents contamination from an active layer, reduces contact resistance between a pixel electrode and the source/drain electrodes, smoothly supplies hydrogen to the active layer and has high mobility, on-current characteristics, and threshold voltage characteristics The TFT includes an active layer having a channel region and source/drain regions, a gate electrode supplying a signal to the channel region, source/drain electrodes respectively connected to the source/drain regions and including at least one of Ti, a Ti alloy, Ta, and a Ta alloy; and an insulating layer interposed between the source/drain electrodes and the active layer and including silicon nitride.

1 . A Thin Film Transistor (TFT) comprising: 
 an active layer having a channel region and source/drain regions;    a gate electrode adapted to supply a signal to the channel region;    source/drain electrodes respectively connected to the source/drain regions and including at least one of Ti, Ti alloy, Ta, and Ta alloy; and    an insulating layer interposed between the source/drain electrodes and the active layer and including silicon nitride.    
     
     
         2 . The TFT of  claim 1 , wherein the source/drain electrodes comprise a first metallic layer pattern, a second metallic layer pattern, and a third metallic layer pattern, the metallic layer patterns being sequentially stacked in the direction of the active layer.  
     
     
         3 . The TFT of  claim 2 , wherein the first metallic layer pattern comprises at least one of Cr, a Cr alloy, Mo, and an Mo alloy.  
     
     
         4 . The TFT of  claim 2 , wherein the second metallic layer pattern comprises at least one of Al, AlSi, AlNd, and AlCu.  
     
     
         5 . The TFT of  claim 2 , wherein the third metallic layer pattern comprises at least one of Ti, a Ti alloy, Ta, and a Ta alloy.  
     
     
         6 . The TFT of  claim 2 , wherein the first metallic layer pattern comprises at least one of Ti, a Ti alloy, Ta, and a Ta alloy.  
     
     
         7 . The TFT of  claim 3 , further comprising a protective layer pattern arranged between the first metallic layer pattern and the second metallic layer pattern.  
     
     
         8 . The TFT of  claim 7 , wherein the protective layer pattern comprises at least one of Ti, a Ti alloy, Ta, and a Ta alloy.  
     
     
         9 . The TFT of  claim 1 , wherein the insulating layer covers the gate electrode.  
     
     
         10 . The TFT of  claim 1 , wherein the insulating layer is interposed between the gate electrode and the active layer.  
     
     
         11 . The TFT of  claim 1 , wherein the active layer comprises polycrystalline silicon.  
     
     
         12 . A flat panel display including a Thin Film Transistor (TFT), the TFT comprising: 
 an active layer having a channel region and source/drain regions;    a gate electrode adapted to supply a signal to the channel region;    source/drain electrodes respectively connected to the source/drain regions and including at least one of Ti, Ti alloy, Ta, and Ta alloy; and    an insulating layer interposed between the source/drain electrodes and the active layer and including silicon nitride.    
     
     
         13 . A method of manufacturing a Thin Film Transistor (TFT), the method comprising: 
 forming an active layer and a gate electrode insulated from each other by a gate insulating layer on a substrate and forming an InterLevel Dielectric (ILD) layer to cover the active layer and the gate electrode, at least one of the gate insulating layer and the ILD layer containing silicon nitride;    thermally treating the substrate;    forming source/drain contact holes in at least one of the gate insulating layer and the ILD layer; and    forming source/drain electrodes, the source/drain electrodes being arranged on the ILD layer, contacting the active layer through the source/drain contact holes, and including at least one of Ti, a Ti alloy, Ta, and a Ta alloy.    
     
     
         14 . The method of  claim 13 , wherein forming the source/drain electrodes comprises forming a first metallic layer pattern, a second metallic layer pattern, and a third metallic layer pattern arranged on the ILD layer and contacting the active layer through the source/drain contact holes.  
     
     
         15 . The method of  claim 13 , wherein forming the source/drain electrodes comprises: 
 stacking a first metallic layer on an entire surface of the substrate including the active layer exposed through the source/drain contact holes;    patterning the first metallic layer to form a first metallic layer pattern;    sequentially stacking a second metallic layer and a third metallic layer on the first metallic layer pattern; and    patterning the second metallic layer and the third metallic layer to form a second metallic layer pattern and a third metallic layer pattern.    
     
     
         16 . The method of  claim 13 , wherein forming the source/drain electrodes comprises: 
 sequentially stacking a first metallic layer, a second metallic layer, and a third metallic layer on an entire surface of the substrate including the active layer exposed through the source/drain contact holes; and    patterning the first metallic layer, the second metallic layer, and the third metallic layer to form a first metallic layer pattern, a second metallic layer pattern, and a third metallic layer pattern.    
     
     
         17 . The method of  claim 14 , wherein the first metallic layer pattern comprises at least one of Cr, a Cr alloy, Mo, and a Mo alloy.  
     
     
         18 . The method of  claim 14 , wherein the second metallic layer pattern comprises at least one of Al, AlSi, AlNd, and AlCu.  
     
     
         19 . The method of  claim 14 , wherein the third metallic layer pattern comprises at least one of Ti, a Ti alloy, Ta, and a Ta alloy.  
     
     
         20 . The method of  claim 14 , wherein the first metallic layer pattern comprises at least one of Ti, a Ti alloy, Ta, and a Ta alloy.  
     
     
         21 . The method of  claim 17 , further comprising forming a protective layer pattern on a first metallic layer pattern before forming the second metallic layer pattern.  
     
     
         22 . A method of manufacturing a flat panel display, the method comprising: 
 manufacturing a Thin Film Transistor (TFT) including: 
 forming an active layer and a gate electrode insulated from each other by a gate insulating layer on a substrate and forming an InterLevel Dielectric (ILD) layer to cover the active layer and the gate electrode, at least one of the gate insulating layer and the ILD layer containing silicon nitride;  
 thermally treating the substrate;  
 forming source/drain contact holes in at least one of the gate insulating layer and the ILD layer; and  
 forming source/drain electrodes, the source/drain electrodes being arranged on the ILD layer, contacting the active layer through the source/drain contact holes, and including at least one of Ti, a Ti alloy, Ta, and a Ta alloy;  
   forming an insulating layer to cover the TFT; and    forming a pixel electrode connected to the source/drain electrodes of the TFT on the insulating layer.