Data processing apparatus and method

Abstract

A data processing apparatus may include a memory unit which stores information including sync frame data, a preceding calculation system circuit which makes a syndrome calculation from the information including sync frame data, a retry calculation system circuit which makes a syndrome calculation from information stored in the memory unit, a buffer group which stores a calculation result of the preceding calculation system circuit or that of the retry calculation system circuit, and a correction execution process system circuit which executes error correction for the information including sync frame data according to the calculation result stored in the buffer group.

1 . A data processing apparatus comprising: 
 a memory unit configured to store information including sync frame data;    a preceding calculation system circuit configured to make a syndrome calculation from the information including sync frame data;    a retry calculation system circuit configured to make a syndrome calculation from information stored in the memory unit;    a buffer group configured to store a calculation result of the preceding calculation system circuit or a calculation result of the retry calculation system circuit; and    a correction execution process system circuit configured to execute error correction for the information including sync frame data according to the calculation result stored in the buffer group.    
   
   
       2 . A disc drive device comprising: 
 a motor configured to rotate a disc on which sync frame data is recorded;    a demodulation circuit system configured to demodulate information including the sync frame data from the disc rotated by the motor;    a memory unit configured to store the information demodulated by the demodulation circuit system;    a preceding calculation system circuit configured to make a syndrome calculation from the information demodulated by the demodulation circuit system;    a retry calculation system circuit configured to make a syndrome calculation from information stored in the memory unit;    a buffer group configured to store a calculation result of the preceding calculation system circuit or a calculation result of the retry calculation system circuit; and    a correction execution process system circuit configured to execute error correction for the information demodulated by the demodulation circuit system according to the calculation result stored in the buffer group.    
   
   
       3 . A device according to  claim 1 , wherein information which is to undergo calculations of the preceding calculation system circuit and the retry calculation system circuit is information corresponding to an ECC block including PI and PO parity data, 
 the preceding calculation system circuit includes a syndrome calculation circuit corresponding to the PI parity data and a syndrome calculation circuit corresponding to the PO parity data,    the retry calculation system circuit includes a syndrome calculation circuit corresponding to the PI parity data and a syndrome calculation circuit corresponding to the PO parity data, and    the buffer group includes a PI buffer configured to store a syndrome calculation result of the information corresponding to the PI parity data, and a PO buffer configured to store a syndrome calculation result of the information corresponding to the PO parity data.    
   
   
       4 . A device according to  claim 1 , further comprising a system controller configured to parallel execute a process upon making the calculation of the retry calculation system circuit for an i-th ECC block and another process upon making the calculation of the preceding calculation system circuit for an (i+1)-th ECC block, where i is an integer number.  
   
   
       5 . A device according to  claim 1 , further comprising a system controller in which when the sync frame data has been duplicated, a preceding calculation result valid mode that gives priority to first arrived duplicated sync frame data, and a retry calculation result valid mode that gives priority to second arrived duplicated sync frame data are set, wherein 
 the correction execution process system circuit uses the calculation result of the preceding calculation system circuit in the preceding calculation result valid mode, and    the correction execution process system circuit uses the calculation result of the retry calculation system circuit in the retry calculation result valid mode.    
   
   
       6 . A device according to  claim 1 , further comprising a system controller configured to inspect whether the sync frame data has been duplicated, and control the correction execution process system circuit to use the calculation result of the retry calculation system circuit in place of the calculation result of the preceding calculation system circuit if duplication is found.  
   
   
       7 . A device according to  claim 6 , wherein the system controller is configured to control the correction execution process system circuit to use the calculation result of the preceding calculation system circuit if no duplication is found.  
   
   
       8 . A data processing method of performing an ECC process using information of sync frames that arrive successively, comprising: 
 executing, if the information of the sync frames does not suffer any duplication, the ECC process using the sync frame information in an arrival order; and    executing, if the information of the sync frames suffers duplication, the ECC process using a second arrived sync frame of the information of duplicated sync frames.    
   
   
       9 . A method according to  claim 8 , wherein the information of the sync frames can undergo syndrome calculation processes by a preceding calculation system and a retry calculation system, and the syndrome calculation process of the preceding calculation system and the syndrome calculation process of the retry calculation system undergo a parallel process at least partially.  
   
   
       10 . A device according to  claim 2 , wherein information which is to undergo calculations of the preceding calculation system circuit and the retry calculation system circuit is information corresponding to an ECC block including PI and PO parity data, 
 the preceding calculation system circuit includes a syndrome calculation circuit corresponding to the PI parity data and a syndrome calculation circuit corresponding to the PO parity data,    the retry calculation system circuit includes a syndrome calculation circuit corresponding to the PI parity data and a syndrome calculation circuit corresponding to the PO parity data, and    the buffer group includes a PI buffer configured to store a syndrome calculation result of the information corresponding to the PI parity data, and a PO buffer configured to store a syndrome calculation result of the information corresponding to the PO parity data.    
   
   
       11 . A device according to  claim 2 , further comprising a system controller configured to parallel execute a process upon making the calculation of the retry calculation system circuit for an i-th ECC block and another process upon making the calculation of the preceding calculation system circuit for an (i+1)-th ECC block, where i is an integer number.  
   
   
       12 . A device according to  claim 2 , further comprising a system controller in which when the sync frame data has been duplicated, a preceding calculation result valid mode that gives priority to first arrived duplicated sync frame data, and a retry calculation result valid mode that gives priority to second arrived duplicated sync frame data are set, wherein 
 the correction execution process system circuit uses the calculation result of the preceding calculation system circuit in the preceding calculation result valid mode, and    the correction execution process system circuit uses the calculation result of the retry calculation system circuit in the retry calculation result valid mode.    
   
   
       13 . A device according to  claim 2 , further comprising a system controller configured to inspect whether the sync frame data has been duplicated, and control the correction execution process system circuit to use the calculation result of the retry calculation system circuit in place of the calculation result of the preceding calculation system circuit if duplication is found.  
   
   
       14 . A device according to  claim 13 , wherein the system controller is configured to control the correction execution process system circuit to use the calculation result of the preceding calculation system circuit if no duplication is found.