US2006006390A1PendingUtilityA1

Polysilicon structure, thin film transistor panel using the same, and manufacturing method of the same

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Assignee: AU OPTRONICS CORPPriority: Jul 9, 2004Filed: Nov 30, 2004Published: Jan 12, 2006
Est. expiryJul 9, 2024(expired)· nominal 20-yr term from priority
Inventors:Chien-Chou HsuTsung-Yi Hsu
H10P 14/3816H10P 14/3806H10P 14/3456H10P 14/3411H10P 14/3814H10D 86/427H10D 86/0227H10D 86/60H10D 62/40H10D 62/10
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Claims

Abstract

A method for forming a polysilicon structure is provided. An amorphous silicon structure with a first amorphous silicon region and a second amorphous silicon region is formed in a first region and a second region of a substrate, respectively. The first amorphous silicon region is thinner than the second amorphous silicon region. The amorphous silicon structure is crystallized to form the polysilicon structure with a first polysilicon region and a second polysilicon region corresponding to the first amorphous silicon region and the second amorphous silicon region.

Claims

exact text as granted — not AI-modified
1 . A polysilicon structure comprising: 
 a substrate; and    a polysilicon layer formed on the substrate, wherein the polysilicon layer comprises a first region and a second region, wherein the thickness of the first region is smaller than the thickness of the second region, and a grain size of the first region is larger than a grain size of the second region.    
   
   
       2 . The polysilicon structure as claimed in  claim 1 , wherein the difference in thickness between the first region and the second region is about 100 to 1000 Å.  
   
   
       3 . The polysilicon structure as claimed in  claim 1 , wherein the difference in thickness between the first region and the second region is about 200 to 400 Å.  
   
   
       4 . The polysilicon structure as claimed in  claim 1 , wherein the first region has a surface roughness higher than that of the second region.  
   
   
       5 . The polysilicon structure as claimed in  claim 1 , wherein the polysilicon layer further comprises a third region, and the thickness of the third region is between those of the first region and the second region.  
   
   
       6 . The polysilicon structure as claimed in  claim 5 , wherein a grain size of the third region is between those of the first region and the second region.  
   
   
       7 . The polysilicon structure as claimed in  claim 5 , wherein the third polysilicon region has a surface roughness between those of the first and second polysilicon regions.  
   
   
       8 . A method for forming a polysilicon structure, comprising: 
 providing a substrate having a first region and a second region;    forming an amorphous silicon structure on the substrate with a first amorphous silicon region in the first region and a second amorphous silicon region in the second region, wherein the first amorphous silicon region is thinner than the second amorphous silicon region; and    crystallizing the amorphous silicon structure to form the polysilicon structure with a first polysilicon region and a second polysilicon region corresponding to the first amorphous silicon region and the second amorphous silicon region, respectively.    
   
   
       9 . The method as claimed in  claim 8 , wherein the formation of the amorphous silicon structure further comprises: 
 forming a first amorphous silicon layer in the second region; and    forming a second amorphous silicon layer in the first region and covering the first amorphous silicon layer.    
   
   
       10 . The method as claimed in  claim 9 , wherein the first amorphous silicon layer is formed by chemical vapor deposition.  
   
   
       11 . The method as claimed in  claim 9 , wherein the second amorphous silicon layer is formed by chemical vapor deposition.  
   
   
       12 . The method as claimed in  claim 8 , wherein the formation of the amorphous silicon structure further comprises: 
 forming a first amorphous silicon layer in the first and second regions;    partially removing the first amorphous silicon layer in the first region; and    forming a second amorphous silicon layer on the partially removed first amorphous silicon layer.    
   
   
       13 . The method as claimed in  claim 12 , wherein the first amorphous silicon layer is formed by chemical vapor deposition.  
   
   
       14 . The method as claimed in  claim 12 , wherein the first amorphous silicon layer in the first region is partially removed by etching.  
   
   
       15 . The method as claimed in  claim 12 , wherein the second amorphous silicon layer is formed by chemical vapor deposition.  
   
   
       16 . The method as claimed in  claim 8 , wherein the crystallizing comprises a laser treatment.  
   
   
       17 . The method as claimed in  claim 16 , wherein the laser treatment employs an excimer laser, continuous wave laser, or laser beam pulse.  
   
   
       18 . The method as claimed in  claim 16 , wherein the laser treatment comprises lateral solidification, sequential lateral solidification, continuous grain silicon, or metal induced lateral crystallization.  
   
   
       19 . A method for forming a polysilicon structure, comprising: 
 providing a substrate having a first region, a second region, and a third region;    forming an amorphous silicon structure on the substrate with a first amorphous silicon region in the first region, a second amorphous silicon region in the second region, and a third amorphous silicon region in the third region, wherein the first amorphous silicon region is thinner than the second amorphous silicon region which is thinner than the third amorphous silicon region; and    crystallizing the amorphous silicon structure to form the polysilicon structure with a first polysilicon region, a second region, and a third polysilicon region corresponding to the first amorphous silicon region, a second amorphous silicon region, and a third amorphous silicon region, respectively.    
   
   
       20 . The method as claimed in  claim 19 , wherein the difference in thickness between the first polysilicon region and the third polysilicon region is about 100 to 1000 Å.  
   
   
       21 . The method as claimed in  claim 19 , wherein the difference in thickness between the first polysilicon region and the third polysilicon region is about 200 to 400 Å.  
   
   
       22 . The method as claimed in  claim 19 , wherein the difference in thickness between the first polysilicon region and the second polysilicon region is about 100 to 1000 Å.  
   
   
       23 . The method as claimed in  claim 19 , wherein the difference in thickness between the first polysilicon region and the second polysilicon region is about 200 to 400 Å.  
   
   
       24 . The method as claimed in  claim 19 , wherein the difference in thickness between the second polysilicon region and the third polysilicon region is about 100 to 1000 Å.  
   
   
       25 . The method as claimed in  claim 19 , wherein the difference in thickness between the second polysilicon region and the third polysilicon region is about 200 to 400 Å.  
   
   
       26 . The method as claimed in  claim 19 , wherein the first polysilicon region has a grain size larger than that of the second polysilicon region which has a grain size larger than that of the third polysilicon region.  
   
   
       27 . The method as claimed in  claim 19 , wherein the first polysilicon region has a surface roughness higher than that of the second polysilicon region which has a surface roughness higher than that of the third polysilicon region.  
   
   
       28 . The method as claimed in  claim 19 , wherein the crystallizing comprises a laser treatment.  
   
   
       29 . The method as claimed in  claim 28 , wherein the laser treatment employs an excimer laser, continuous wave laser, or laser beam pulse.  
   
   
       30 . The method as claimed in  claim 28 , wherein the laser treatment comprises lateral solidification, sequential lateral solidification, continuous grain silicon, or metal induced lateral crystallization.  
   
   
       31 . A thin film transistor panel, comprising: 
 a substrate;    a first transistor disposed on the substrate and comprising a first polysilicon region serving as a first active region; and    a second transistor disposed on the substrate and comprising a second polysilicon region serving as a second active region;    wherein the first polysilicon region is thinner than the second polysilicon region and a grain size of the first polysilicon region is larger than that of the second polysilicon region.    
   
   
       32 . The panel as claimed in  claim 31 , wherein the difference in thickness between the first polysilicon region and the second polysilicon region is about 100 to 1000 Å.  
   
   
       33 . The panel as claimed in  claim 31 , wherein the difference in thickness between the first polysilicon region and the second polysilicon region is about 200 to 400 Å.  
   
   
       34 . The panel as claimed in  claim 31 , wherein the first polysilicon region has a surface roughness higher than that of the second polysilicon region.

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