Double-cell memory device

Abstract

A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the gate structure lines. A plurality of second doped regions, in the substrate at a side of a last line of the gate structure lines. Wherein the first doped regions and the second doped regions respectively for a plurality of pairs of doped region with respect to a plurality of bit lines. In other words, the conventional source/drain regions for each memory cell are saved. Instead, the gate lines are adjacently disposed together.

1 - 24 . (canceled)  
     
     
         25 . An operation method for a string structure, the string structure comprising a first doped region and a second doped region in a substrate, wherein the first doped region and the second doped region are respectively coupled to a bit line and a source voltage; a plurality of selection gates over the substrate between the first doped region and the second doped region, wherein a first one of the selection gates is adjacent to the first dope region; and a plurality of stack-gate structures, over the substrate between the selection gates, wherein the stack-gate structures respectively coupled to word lines, 
 the method comprising: 
 an erasing operation, wherein a selected one of the world lines and the substrate are applied an erasing voltage;  
 a programming operation, wherein one of the doped regions is applied with a ground voltage while the other one of the doped region is applied with a first positive voltage, the word lines are applied by a second positive voltage, the selection gate are applied with a passing voltage except a selected one of the selection gates, which is at a side of a selected one of the word lines, wherein the selected one of the selection gates is applied by a voltage equal to or slightly greater than a threshold voltage; and  
 a read operation, wherein a selected one of the word lines is applied with a reading voltage while the selection gates are applied with a positive voltage, and the bit line is applied with a bit-line voltage.