Defect-free thin and planar film processing

Abstract

The process of the present invention forms copper interconnects in a semiconductor wafer surface. During the process, initially, narrow and large features are provided in the top surface of the wafer, and then a primary copper layer is deposited by employing an electrochemical deposition process. The primary copper layer completely fills the features and forms a planar surface over the narrow feature and a non-planar surface over the large feature. By employing an electrochemical mechanical deposition process, a secondary copper layer is deposited onto the primary copper layer to form a planar copper layer over the narrow and large features. After this process step, the thickness of the planar copper layer is reduced using an electropolishing process.

1 . A system for forming conductive structures on a semiconductor wafer having a top surface with a first feature and a second feature disposed therein, the first feature having a first width and the second feature having the widest width, the system comprising: 
 an electrochemical deposition module configured to completely fill the first feature and the second feature with a first conductive layer; and    an electrochemical mechanical deposition module configured to deposit a second conductive layer over the first conductive layer and form a planar conductive layer.    
     
     
         2 . The system of  claim 1 , wherein the electrochemical deposition module includes a first electrolyte solution having a first additive composition and the electrochemical mechanical deposition module includes a second electrolyte solution having a second additive composition.  
     
     
         3 . The system of  claim 1  further comprising a chemical mechanical polishing (CMP) module configured to remove the planar conductive layer from the top surface to electrically isolate the first feature from the second feature.  
     
     
         4 . The system of  claim 1 , wherein the electrochemical deposition module deposits a first conductive layer having a thickness in the second feature that is greater than or equal to a depth of the second feature.  
     
     
         5 . The system of  claim 1  further comprising an annealing module to anneal the conductive layer.  
     
     
         6 . The system of  claim 1 , wherein the conductive layer includes copper.  
     
     
         7 . The system of  claim 1  further comprising an electropolishing module configured to reduce a thickness of the planar conductive layer.  
     
     
         8 . The system of  claim 7 , wherein the electropolishing module removes substantially all of the planar conductive layer.  
     
     
         9 . The system of  claim 7  further comprising a chemical mechanical polishing (CMP) module configured to remove the planar conductive layer from the top surface to electrically isolate the first feature from the second feature.  
     
     
         10 . A system for forming conductive structures on a semiconductor wafer having a top surface with a first feature and a second feature disposed therein, the first feature having a first width and the second feature having the widest width, the system comprising: 
 a deposition module configured to completely fill the first feature and the second feature with a first conductive layer and to deposit a second conductive layer over the first conductive layer to form a planar conductive layer,    
     
     
         11 . The system of  claim 10 , wherein the deposition module deposits a first conductive layer having a thickness in the second feature that is greater than or equal to a depth of the second feature.  
     
     
         12 . The system of  claim 10  further comprising a chemical mechanical polishing (CMP) module configured to remove the conductive layer from the top surface to electrically isolate the first feature from the second feature.  
     
     
         13 . The system of  claim 10  further comprising an electropolisbing module configured to reduce a thickness of the planar conductive layer.  
     
     
         14 . The system of  claim 13  further comprising a chemical mechanical polishing (CMP) module configured to remove the planar conductive layer to electrically isolate the first feature from the second feature.