Highly concurrent DMA controller with programmable DMA channels

Abstract

A data transaction controller for transferring data responsive to a request from a client. The data transaction controller includes channel circuitry for providing a channel for data transfers. The channel circuitry includes a first storage device for storing channel configuration data. The data transaction controller further includes control circuitry for controlling access by the client to the channel circuitry.

1 . A computer system comprising: 
 a mass storage device;    a first data transfer controller for controlling data transfers involving the mass storage device, the first data transfer controller operable in a channel free state and a channel unavailable state;    a circuit device connected to the first data transfer controller, the circuit device for requesting a particular data transfer to be controlled by the first data transfer controller; and    a second data transfer controller connected to the circuit device, the second data transfer controller for controlling data transfers and for controlling the particular data transfer responsive, at least, to the circuit device receiving an indication that the first data transfer controller is in the channel unavailable state.    
     
     
         2 . The computer system of  claim 1 , wherein the circuit device is a non-host processor entity.  
     
     
         3 . The computer system of  claim 1 , wherein the circuit device is a microprocessor.  
     
     
         4 . The computer system of  claim 1 , wherein the second data transfer controller is associated with a memory address and wherein the first data transfer controller, when in the channel unavailable state, is configured to provide the circuit device with the memory address for the second data transfer controller.  
     
     
         5 . The computer system of  claim 1 , wherein the first data transfer controller includes a storage device for storing an indication of whether the first data transfer controller is in the channel free state or in the channel unavailable state.  
     
     
         6 . The computer system of  claim 5 , wherein the client is configured to read the indication from the storage device and further wherein responsive to the indication indicating that the first data transfer controller is in the channel unavailable state, request the particular data transfer to be controlled by the second data transfer controller.  
     
     
         7 . The computer system of  claim 1 , wherein the first data transfer controller is operable in one of a client queuing mode and a channel queuing mode.  
     
     
         8 . The computer system of  claim 1 , wherein the first data transfer controller is operable in a data streaming mode.  
     
     
         9 . The computer system of  claim 8 , wherein the first data transfer controller is operable in one of a RAM channel mode and a FIFO channel mode.  
     
     
         10 . The computer system of  claim 1 , wherein the mass storage device is a hard drive.  
     
     
         11 . A data transfer controller for transferring data responsive to a request from a client, the data transfer controller comprising: 
 a first channel circuitry for providing a first channel for data transfers, the channel circuitry operable in a plurality of modes;    a storage device connected to the first channel circuitry, the storage device for storing an indication of a particular one of the plurality of modes; and    a control circuitry connected to the channel circuitry, the control circuitry for controlling provision of the first channel to the client;    wherein the channel circuitry is operable in the particular one of the plurality of modes.    
     
     
         12 . The data transfer controller of  claim 11 , wherein the first channel is configurable in a one of a client queuing mode and a channel queuing mode, and further wherein the storage device is for storing an indication that the first channel is in one of the client queuing mode and the channel queuing mode.  
     
     
         13 . The data transfer controller of  claim 11 , wherein the first channel is configurable in a descriptor stream mode.  
     
     
         14 . The data transfer controller of  claim 11  included in one of a bridge and an I/O device.  
     
     
         15 . The data transfer controller of  claim 11  included in a memory controller.  
     
     
         16 . A DMA controller comprising: 
 a first channel device for performing a first DMA transaction, the first channel device operable in a first mode; and    a second channel device for performing a second DMA transaction, the second channel device operable in a second mode;    wherein the first mode and the second mode are different and wherein the first DMA transaction and the second DMA transaction are different.    
     
     
         17 . The DMA controller of  claim 16 , further comprising a control device connected to the first channel device and the second channel device, the control device for controlling an acquisition of the first channel device responsive to a request for a DMA transaction from a client.  
     
     
         18 . The DMA controller of  claim 16 , further comprising: 
 a first address translation mechanism associated with the first channel device; and    a second address translation mechanism associated with the second channel device, the second address translation mechanism operable independent of the first address translation mechanism.    
     
     
         19 . The DMA controller of  claim 16 , wherein the first mode is one of client queuing mode and channel queuing mode.  
     
     
         20 . The DMA controller of  claim 16 , wherein the second mode is one of descriptor stream mode, FIFO channel mode and RAM channel mode.  
     
     
         21 . A computer system comprising: 
 a first memory configured to store a data transfer instruction;    a second memory connected to the first memory, the second memory for storing an indication of the data transfer instruction, the indication indicating a request for performance of the data transfer instruction; and    a data transfer controller connected to the second memory, the data transfer controller for controlling a data transfer responsive to the second memory receiving the indication of the data transfer instruction.    
     
     
         22 . The computer system of  claim 21 , further comprising a third memory connected to the data transfer controller, the third memory for storing a transaction base indicating a location in memory of the first memory.  
     
     
         23 . The computer system of  claim 22 , wherein the third memory is located proximate the data transfer controller.  
     
     
         24 . The computer system of  claim 23 , wherein the third memory is I/O memory mapped.  
     
     
         25 . The computer system of  claim 21 , wherein the third memory is for storing a response data field and a response address field.  
     
     
         26 . The computer system of  claim 21 , wherein the first memory is configured to store a descriptor.  
     
     
         27 . A computer system comprising: 
 a first means configured to store a data transfer instruction;    a second means connected to the first means, the second means for storing an indication of the data transfer instruction, the indication indicating a request for performance of the data transfer instruction; and    a data transfer means connected to the second means, the data transfer means for controlling a data transfer responsive to the second means receiving the indication of the data transfer instruction.    
     
     
         28 . The computer system of  claim 27 , further comprising a third means connected to the data transfer means, the third means for storing a transaction base indicating a location in memory of the first means.  
     
     
         29 . The computer system of  claim 28 , wherein the third means is located proximate the data transfer means.  
     
     
         30 . The computer system of  claim 29 , wherein the third means is I/O memory mapped.  
     
     
         31 . The computer system of  claim 27 , wherein the third means is for storing a response data field and a response address field.  
     
     
         32 . The computer system of  claim 27 , wherein the first means is configured to store a descriptor.  
     
     
         33 . A computer system comprising: 
 a mass storage means;    a first data transfer means for controlling data transfers involving the mass storage means, the first data transfer means operable in a channel free state and a channel unavailable state;    a logical means connected to the first data transfer means, the logical means for requesting a particular data transfer to be controlled by the first data transfer means; and    a second data transfer means connected to the logical means, the second data transfer means for controlling data transfers and for controlling the particular data transfer responsive, at least, co the logical means receiving an indication that the first data transfer means is it the channel unavailable state.    
     
     
         34 . The computer system of  claim 33 , wherein the second data transfer means is associated with a memory address and wherein the first data transfer means, when in the channel unavailable state, is configured to provide the logical means with the memory address for the second data transfer means.  
     
     
         35 . The computer system of  claim 33 , wherein the first data transfer means includes a storage means for storing an indication of whether the first data transfer means is in the channel free state or in the channel unavailable state.  
     
     
         36 . The computer system of  claim 35 , wherein the client is configured to read the indication from the storage means and further wherein responsive to the indication indicating that the first data transfer means is in the channel unavailable state, request the particular data transfer to be controlled by the second data transfer means.  
     
     
         37 . The computer system of  claim 33 , wherein the first data transfer means is operable in one of a client queuing mode and a channel queuing mode.  
     
     
         38 . The computer system of  claim 33 , wherein the first data transfer means is operable in a data streaming mode.  
     
     
         39 . The computer system of  claim 38 , wherein the first data transfer means is operable in one of a RAM channel mode and a FIFO channel mode.  
     
     
         40 . A method for transferring data using a controller including a channel, the channel being operable in a plurality of data transfer modes, the method comprising the steps of: 
 requesting control of the channel;    responsive to receiving control of the channel, configuring the channel to be operable in a particular one of the plurality of modes; and    requesting data to be transferred through the channel.    
     
     
         41 . The method of  claim 40 , further comprising the step of releasing the control of the channel.  
     
     
         42 . The method of  claim 40 , wherein the plurality of data transfer modes includes a software queuing mode and a client queuing mode.  
     
     
         43 . The method of  claim 42 , wherein the plurality of data transfer modes includes a descriptor streaming mode.  
     
     
         44 . The method of  claim 42 , wherein the plurality of data transfer modes includes FIFO channel mode and RAM channel mode.