Memory system and method having selective ECC during low power refresh

Abstract

A computer system includes a processor coupled to a DRAM through a memory controller. The processor switches the DRAM to a low power refresh mode in which DRAM cells are refreshed at a sufficiently low rate that data retention errors may occur. Prior to switching the DRAM to the low power refresh mode, the processor identifies a region of an array of DRAM cells that contains essential data that needs to be protected from such data retention errors. The processor then reads data from the identified region, and either the DRAM or the memory controller generates error checking and correcting syndromes from the read data. The syndromes are stored in the DRAM, and the low power refresh mode is then entered. Upon exiting the low power refresh mode, the processor again reads the data from the identified region, and the read data is checked and corrected using the syndromes.

1 . In a computer system having a processor coupled to a dynamic random access memory (“DRAM”) device, a method of reducing the power consumed by the DRAM device, comprising: 
 refreshing DRAM cells in the DRAM device at a first rate when the DRAM device is active;    refreshing the DRAM cells in the DRAM device at a second rate when the DRAM device is inactive, the second rate being substantially slower than the first rate;    prior to transitioning from the first rate to the second rate, transitioning to an ECC protection mode by: 
 determining which DRAM cells are storing data that should be protected from data retention errors;  
 reading data from the DRAM cells determined to be storing data that should be protected;  
 generating ECC syndromes corresponding to the read data; and  
 storing the generated syndromes; and  
   when transitioning from the second rate to the first rate, transitioning from the ECC protection mode by: 
 reading data from the DRAM cells that are storing data that should be protected;  
 reading the stored ECC syndromes corresponding to the read data;  
 using the syndromes to determine if any of the read data are in error;  
 correcting any read data found to be in error; and  
 storing the corrected data in the DRAM cells.  
   
     
     
         2 . The method of  claim 1  wherein the act of determining which DRAM cells are storing data that should be protected from data retention errors comprises determining which DRAM cells are storing data that should be protected from data retention errors based on a record of the location of the DRAM cells.  
     
     
         3 . The method of  claim 1  wherein the act of determining which DRAM cells are storing data that should be protected from data retention errors comprises determining which DRAM cells are storing data that should be protected from data retention errors based on a record of the data stored in the DRAM cells.  
     
     
         4 . The method of  claim 1  wherein the act of determining which DRAM cells are storing data that should be protected from data retention errors comprises using the processor to determine which DRAM cells are storing data that should be protected from data retention errors.  
     
     
         5 . The method of  claim 1  wherein the act of reading data from the DRAM cells determined to be storing data that should be protected prior to transitioning from the first rate to the second rate comprises reading the data in a burst read operation.  
     
     
         6 . The method of  claim 1  wherein the act of reading data from the DRAM cells determined to be storing data that should be protected when transitioning to the ECC protection mode comprises using the processor to read the data from the DRAM cells determined to be storing data that should be protected.  
     
     
         7 . The method of  claim 1  wherein the act of reading data from the DRAM cells determined to be storing data that should be protected when transitioning to the ECC protection mode comprises initiating and controlling a read operation from within the DRAM device without using the processor.  
     
     
         8 . The method of  claim 1  wherein the act of generating ECC syndromes corresponding to the read data comprises generating the ECC syndromes within the DRAM device.  
     
     
         9 . The method of  claim 1  wherein the system further comprises a memory controller coupling the processor to the DRAM device, and wherein the act of generating ECC syndromes corresponding to the read data comprises generating the ECC syndromes within the memory controller.  
     
     
         10 . The method of  claim 1  wherein the act of storing the generated syndromes comprises storing the generated syndromes within the DRAM device.  
     
     
         11 . The method of  claim 10  wherein the act of storing the generated syndromes within the DRAM device comprises storing the generated syndromes in DRAM cells.  
     
     
         12 . The method of  claim 1  wherein the act of reading data from the DRAM cells that are storing data that should be protected when transitioning from the ECC protection mode comprises reading the data in a burst read operation.  
     
     
         13 . The method of  claim 1  wherein the act of reading data from the DRAM cells that are storing data that should be protected when transitioning from the ECC protection mode comprises using the processor to read the data from the DRAM cells that are storing data that should be protected.  
     
     
         14 . The method of  claim 1  wherein the act of reading data from the DRAM cells that are storing data that should be protected when transitioning from the ECC protection mode comprises initiating and controlling a read operation from within the DRAM device without using the processor.  
     
     
         15 . The method of  claim 1  wherein the act of reading the stored ECC syndromes corresponding to the data read when transitioning from the ECC protection mode comprises reading the stored ECC syndromes from the DRAM device.  
     
     
         16 . The method of  claim 1  wherein the act of using the syndromes to determine if any of the read data are in error comprises determining if any of the read data are in error within the DRAM device using the syndromes.  
     
     
         17 . The method of  claim 1  wherein the system further comprises a memory controller coupling the processor to the DRAM device, and wherein the act of using the syndromes to determine if any of the read data are in error comprises determining if any of the read data are in error within the memory controller using the syndromes.  
     
     
         18 . The method of  claim 1  wherein the act of correcting any read data found to be in error comprises using the DRAM device to correct any read data found to be in error.  
     
     
         19 . The method of  claim 1  wherein the system further comprises a memory controller coupling the processor to the DRAM device, and wherein the act of correcting any read data found to be in error comprises using the memory controller to correct any read data found to be in error.  
     
     
         20 . The method of  claim 1  wherein the act of storing the corrected data in the DRAM cells comprises using the processor to store the corrected data in the DRAM cells.  
     
     
         21 . The method of  claim 1  wherein the act of storing the corrected data in the DRAM cells comprises writing the corrected data to the DRAM cells in a burst write operation.  
     
     
         22 . The method of  claim 1  wherein the act of transitioning to an ECC protection mode comprises using the processor to transition to the ECC protection mode.  
     
     
         23 . The method of  claim 1  wherein the DRAM device further comprises a mode register, and wherein the act of using the processor to transition to the ECC protection mode comprises using the processor to store a first mode control bit in the mode register, the first mode control bit corresponding to the ECC protection mode.  
     
     
         24 . The method of  claim 1  wherein the DRAM device further comprises a control register, and wherein the act of using the processor to transition to the ECC protection mode comprises using the processor to store control data in the control register, the control data comprising a first bit enabling the ECC protection mode, and a plurality of second bits that specify the DRAM cells determined to be storing data that should be protected.  
     
     
         25 . The method of  claim 1  wherein the DRAM device further comprises a mode register, and wherein the act of using the processor to transition from the ECC protection mode comprises using the processor to store a second mode control bit in the mode register, the second mode control bit corresponding to a normal operating mode.  
     
     
         26 . The method of  claim 1  wherein the DRAM device further comprises a control register, and wherein the act of using the processor to transition from the ECC protection mode comprises using the processor to store a bit disabling the ECC protection mode.  
     
     
         27 . The method of  claim 1  wherein the acts of reading data from the DRAM cells that are storing data that should be protected, reading the stored ECC syndromes corresponding to the read data, and using the syndromes to determine if any of the read data are in error when transitioning from the second rate to the first rate are performed only for the DRAM cells storing data words to which data will be written to a part of the stored data word.  
     
     
         28 . The method of  claim 27  wherein the acts of reading data from the DRAM cells that are storing data that should be protected, reading the stored ECC syndromes corresponding to the read data, using the syndromes to determine if any of the read data are in error, and correcting any read data found to be in error are performed during normal operation of the DRAM for the DRAM cells storing data words to which data will not be written to a part of the stored data word.  
     
     
         29 . The method of  claim 28 , further comprising providing a tag for each data word that should be protected, the tag indicating whether or not a valid syndrome exists for the corresponding data word.  
     
     
         30 . The method of  claim 29 , further comprising setting the tag for each word to indicate a valid syndrome does not exist for the word when data is written to a part of one of the stored data words.  
     
     
         31 . A method of refreshing memory cells in a dynamic random access memory (“DRAM”) device, the method comprising: 
 refreshing the memory cells at a reduced power rate that is sufficiently slow that data retention errors can be expected to occur during refresh; and    prior to refreshing the memory cells at the reduced power rate, determining which memory cells are storing essential data that should be protected from data retention errors, and use ECC techniques to check and correct the essential data without using ECC techniques to check and correct data stored in other of the memory cells.    
     
     
         32 . The method of  claim 31  wherein the act of using ECC techniques to check and correct the essential data comprises, prior to refreshing the memory cells at the reduced power rate: 
 identifying the memory cells storing essential data;    reading the essential data;    generating syndromes corresponding to the read data; and    storing the generated syndromes.    
     
     
         33 . The method of  claim 32  wherein the act of using ECC techniques to check and correct the essential data comprises, when no longer refreshing the memory cells at the reduced power rate: 
 reading the essential data;    retrieving the stored syndromes;    using the stored syndromes to determine if any of the essential data are in error;    if any of the essential data were found to be in error, using the stored syndromes to provide corrected data; and    storing the corrected data in the memory cells.    
     
     
         34 . The method of  claim 33  wherein the DRAM is coupled to a processor, and wherein the act of reading the essential data comprises using the processor to read the essential data.  
     
     
         35 . The method of  claim 31  wherein the DRAM is coupled to a processor, and wherein the act of determining which memory cells are storing essential data that should be protected comprises using the processor to determine which memory cells are storing essential data that should be protected.  
     
     
         36 . A processor-based system, comprising: 
 a memory controller;    a dynamic random access memory (“DRAM”) device coupled to the memory controller, the DRAM device having a plurality of DRAM cells that are refreshed at a relatively high rate during operation in a normal mode and a relatively low rate during operation in a low power refresh mode; and    a processor coupled to the DRAM device through the memory controller, the processor being operable to couple a first signal to the DRAM device to cause the DRAM device to operate in the low power refresh mode and to couple a second signal to the DRAM device to cause the DRAM device to operate in the normal mode, the processor being operable prior to coupling the first signal to the DRAM device to: 
 determine which DRAM cells are storing data that should be protected from data retention errors in the low power refresh mode;  
 couple signals to the DRAM device that cause data to be read from the DRAM cells determined to be storing data that should be protected, the read data being used to generate ECC syndromes corresponding to the read data and being stored for subsequent use; and  
   the processor being operable after coupling the second signal to the DRAM device to couple signals to the DRAM device that cause data to be read from the DRAM cells that are storing data that should be protected, the read data being checked for errors and any errors corrected using the stored syndromes, the corrected data being stored in the DRAM device.    
     
     
         37 . The system of  claim 36  wherein the DRAM device comprises: 
 a syndrome memory that is operable to store the syndromes; and    ECC logic that is operable to: 
 receive the read data from the DRAM cells;  
 generate ECC syndromes corresponding to the read data;  
 cause the generated syndromes to be stored in the DRAM;  
 use the stored syndromes to check and correct read data from the DRAM cells; and  
 cause the corrected data to be stored in the DRAM.  
   
     
     
         38 . The system of  claim 37  wherein the DRAM device comprises a control register that receives a control bit from the processor, the control register being operable to store the control bit and to enable the ECC logic responsive to the control bit being set.  
     
     
         39 . The system of  claim 38  wherein the control register further receives from the processor a plurality of bits identifying the DRAM cells that are storing data that should be protected from data retention errors.  
     
     
         40 . The system of  claim 37  wherein the DRAM device further comprises: 
 an ECC controller that is operable to controls the ECC logic; and    a mode register coupled to receive mode control signals from the processor, the mode control signals switching the DRAM device between the normal mode and the low power refresh mode, the mode control signals further enabling and disabling the ECC controller.    
     
     
         41 . The system of  claim 37  wherein the DRAM device further comprises data steering logic coupled to receive corrected data from the ECC logic, the data steering logic being operable to couple the corrected data back to the DRAM cells for storage in the DRAM device.  
     
     
         42 . The system of  claim 36  wherein the DRAM device comprises a syndrome memory that is operable to store the generated ECC syndromes corresponding to the read data.  
     
     
         43 . The system of  claim 36  wherein the memory controller comprises ECC logic that is operable to: 
 receive the read data from the DRAM cells;    generate ECC syndromes corresponding to the read data;    cause the generated syndromes to be stored in the DRAM;    use the stored syndromes to check and correct read data from the DRAM cells; and    cause the corrected data to be stored in the DRAM.    
     
     
         44 . A computer system, comprising: 
 a memory controller;    a dynamic random access memory (“DRAM”) device coupled to the memory controller, the DRAM device having at least one array of DRAM cells that are refreshed at a relatively high rate during operation in a normal mode and a relatively low rate during operation in a low power refresh mode; and    a processor coupled to the DRAM device through the memory controller, the processor being operable to identify at least one region of the array that should be protected from data loss when the DRAM device is operating in the low power refresh mode, the processor being operable to protect the identified region using ECC techniques during the period the DRAM device is operating in the low power refresh mode without protecting regions of the array other than the identified region.    
     
     
         45 . The computer system of  claim 44  wherein the DRAM device comprises ECC logic that is operable to generate syndromes corresponding to data stored in the identified regions of the array and to use the syndromes to check and correct the data stored in the identified regions of the array.  
     
     
         46 . The computer system of  claim 44  wherein the memory controller comprises ECC logic that is operable to generate syndromes corresponding to data stored in the identified regions of the array and to use the syndromes to check and correct the data stored in the identified regions of the array.  
     
     
         47 . The system of  claim 46  wherein the DRAM device comprises a syndrome memory that is operable to store the ECC syndromes generated by the memory controller.