Magnetic random access memory with bit line and/or digit line magnetic layers

Abstract

A magnetic random access memory (MRAM) device may include a substrate, a first magnetic layer on the substrate, and a digit line on the first magnetic layer. A magnetic tunnel junction structure may be provided adjacent the digit line, and a bit line may be provided on the magnetic tunnel junction structure such that the magnetic tunnel junction structure is between the bit line and the digit line. In addition, a second magnetic layer may be provided on the bit line.

1 . A magnetic random access memory (MRAM) device comprising: 
 a substrate;    a first magnetic layer on the substrate;    a digit line on the first magnetic layer;    a magnetic tunnel junction structure adjacent the digit line;    a bit line on the magnetic tunnel junction structure such that the magnetic tunnel junction structure is between the bit line and the digit line; and    a second magnetic layer on the bit line.    
     
     
         2 . A magnetic random access memory device according to  claim 1  wherein the magnetic tunnel junction structure includes a synthetic anti-ferromagnetic (SAF) free layer.  
     
     
         3 . A magnetic random access memory device according to  claim 2  wherein the synthetic anti-ferromagnetic (SAF) free layer includes an exchange spacer layer between first and second free layers such that the first free layer is between the exchange spacer layer and the digit line.  
     
     
         4 . A magnetic random access memory device according to  claim 3  wherein the first and second free layers comprises a ferromagnetic material.  
     
     
         5 . A magnetic random access memory device according to  claim 3  wherein the exchange spacer layer comprises ruthenium.  
     
     
         6 . A magnetic random access memory device according to  claim 2  wherein the magnetic tunnel junction structure includes a tunneling insulating layer between the synthetic anti-ferromagnetic free layer and the digit line, a pinned layer between the tunneling insulating layer and the digit line, and a pinning layer between the pinned layer and the digit line.  
     
     
         7 . A magnetic random access memory device according to  claim 6  wherein the pinned layer includes an exchange spacer layer between first and second pinned sub-layers such that the first pinned sub-layer is between the exchange spacer layer and the pinning layer and the second pinned sub-layer is between the exchange spacer layer and the tunneling insulating layer.  
     
     
         8 . A magnetic random access memory device according to  claim 7  wherein the first and second pinned sub-layers comprise a ferromagnetic material.  
     
     
         9 . A magnetic random access memory device according to  claim 1  wherein portions of the first magnetic layer are between the digit line and the substrate and wherein portions of the first magnetic layer extend on sidewalls of the digit line.  
     
     
         10 . A magnetic random access memory device according to  claim 1  wherein the bit line is between portions of the second magnetic layer and the substrate and wherein portions of the second magnetic layer extend on sidewalls of the bit line.  
     
     
         11 . A magnetic random access memory device according to  claim 1  wherein at least one of the first magnetic layer and/or the second magnetic layer comprises a permanent magnet.  
     
     
         12 . A magnetic random access memory device according to  claim 1  wherein at least one of the first magnetic layer and/or the second magnetic layer comprises at least one of Co and/or CoFe.  
     
     
         13 . A magnetic random access memory device according to  claim 1  wherein at least one of the first magnetic layer and/or the second magnetic layer comprises an electromagnet.  
     
     
         14 . A magnetic random access memory device according to  claim 1  wherein a longest dimension of the magnetic tunnel junction structure parallel with respect to a surface of the substrate is arranged non-parallel with respect to the digit line and the bit line.  
     
     
         15 . A magnetic random access memory device according to  claim 1  further comprising: 
 an insulating passivation layer on the bit line such that the bit line is between the insulating passivation layer and the substrate; and    at least two magnets on the insulating passivation layer such that the insulating passivation layer is between the at least two magnets and the substrate.    
     
     
         16 . A magnetic random access memory device according to  claim 15  wherein each of the at least two magnets comprises a permanent magnet and/or an electromagnet.  
     
     
         17 . A magnetic random access memory (MRAM) device comprising: 
 a substrate;    a plurality of digit lines on the substrate;    a plurality of bit lines crossing the plurality of digit lines on the substrate;    a plurality of magnetic tunnel junction structures with each magnetic tunnel junction structure being provide at a junction of respective digit and bit lines and between the respective digit and bit lines;    an insulating passivation layer on the plurality of digit lines, on the plurality of bit lines and on the plurality of magnetic tunnel junction structures such that the plurality of digit lines, the plurality of bit lines and the plurality of magnetic tunnel junction structures are between the insulating passivation layer and the substrate; and    at least two magnets on the insulating passivation layer such that the insulating passivation layer is between the at least two magnets and the substrate.    
     
     
         18 . A magnetic random access memory device according to  claim 17  wherein each of the magnetic tunnel junction structures includes a respective synthetic anti-ferromagnetic free layer.  
     
     
         19 . A magnetic random access memory device according to  claim 18  wherein each of the synthetic anti-ferromagnetic free layers includes an exchange spacer layer between first and second free layers such that the first free layer is between the exchange spacer layer and the substrate and the second free layer is between the exchange spacer layer and the insulating passivation layer.  
     
     
         20 . A magnetic random access memory device according to  claim 19  wherein each of the first and second free layers comprises a ferromagnetic material.  
     
     
         21 . A magnetic random access memory device according to  claim 19  wherein the exchange spacer layer comprises ruthenium.  
     
     
         22 . A magnetic random access memory device according to  claim 18  wherein each of the magnetic tunnel junction structures includes a tunneling insulating layer between the synthetic anti-ferroelectric free layer and the substrate, a pinned layer between the tunneling insulating layer and the substrate, and a pinning layer between the pinned layer and the substrate.  
     
     
         23 . A magnetic random access memory device according to  claim 22  wherein the pined layer includes an exchange spacer layer between first and second pinned sub-layers such that the first pinned sub-layer is between the exchange spacer layer and the pinning layer and the second pinned sub-layer is between the exchange spacer layer and the tunneling insulating layer.  
     
     
         24 . A magnetic random access memory device according to  claim 23  wherein each of the first and second pinned sub-layers comprises a ferroelectric material.  
     
     
         25 . A magnetic random access memory device according to  claim 17  further comprising: 
 a plurality of cladding layers with portions of each cladding layer being provided between a respective digit line and the substrate.    
     
     
         26 . A magnetic random access memory device according to  claim 25  wherein each cladding layer comprises a ferroelectric material.  
     
     
         27 . A magnetic random access memory device according to  claim 17  further comprising: 
 a plurality of cladding layers with portions of each cladding layer being provided between a respective bit line and the insulating passivation layer.    
     
     
         28 . A magnetic random access memory device according to  claim 27  wherein each cladding layer comprises a ferroelectric material.  
     
     
         29 . A magnetic random access memory device according to  claim 17  wherein a longest dimension of each of the magnetic tunnel junction structures parallel with respect to a surface of the substrate is arranged non-parallel with respect to the respective digit and bit lines.  
     
     
         30 . A magnetic random access memory device according to  claim 17  wherein each of the at least two magnets comprises a permanent magnet and/or an electromagnet.  
     
     
         31 . A magnetic random access memory device according to  claim 17  wherein first and second ones of the at least two magnets are orthogonal with respect to each other.  
     
     
         32 . A magnetic random access memory device according to  claim 17  wherein the at least two magnets includes a plurality of pairs of magnets.