Semiconductor constructions and integrated circuits

Abstract

The invention includes a TFT-based logic circuit construction. Such construction includes a pair of first transistor devices, and a pair of second transistor devices over the first transistor devices. The first transistor devices have first active regions extending into a first semiconductive material, and the second transistor devices have second active regions extending into a second semiconductive material. At least one of the first and second semiconductive materials can comprise crystalline Si/Ge. The logic construction can comprise NOR circuitry and/or NAND circuitry, as well as higher level logic cells, such as latches. Further, the logic circuit construction can be associated with a semiconductor-on-insulator structure, and on versatile substrates. The invention includes three-dimensional logic cell layout configurations for enhanced wireability and logic cell density, which can lead to enhanced performance.

1 - 87 . (canceled)  
     
     
         88 . A semiconductor construction, comprising: 
 a first crystalline material which includes silicon and germanium;    a pair of first transistor devices having first active regions extending into the first crystalline material, the first transistor devices sharing a source/drain region;    a conductive interconnect in electrical contact with the shared source/drain region and in electrical connection with a second crystalline material which includes silicon and germanium; and    a pair of second transistor devices having second active regions extending into the second crystalline material.    
     
     
         89 . The construction of  claim 88  wherein the first and second transistor devices are part of a pair of NOR circuits in a cross-coupled latch.  
     
     
         90 . The construction of  claim 88  wherein the first transistor devices are PFET devices and wherein the second transistor devices are NFET devices.  
     
     
         91 . The construction of  claim 88  wherein the first transistor devices are NFET devices and wherein the second transistor devices are PFET devices.  
     
     
         92 . The construction of  claim 88  wherein the first crystalline material is part of an SOI construction supported by a substrate.  
     
     
         93 . The construction of  claim 92  wherein the substrate comprises a semiconductive material.  
     
     
         94 . The construction of  claim 92  wherein the substrate comprises glass.  
     
     
         95 . The construction of  claim 92  wherein the substrate comprises aluminum oxide.  
     
     
         96 . The construction of  claim 92  wherein the substrate comprises silicon dioxide.  
     
     
         97 . The construction of  claim 92  wherein the substrate comprises a metal.  
     
     
         98 . The construction of  claim 92  wherein the substrate comprises a plastic.  
     
     
         99 . The construction of  claim 88  wherein the first crystalline material comprises from about  10  to about  60  atomic percent germanium.  
     
     
         100 . The construction of  claim 88  wherein the second crystalline material comprises from about  10  to about  60  atomic percent germanium.  
     
     
         101 . The construction of  claim 88  wherein the first active regions are entirely contained within a single crystal of the first crystalline material.  
     
     
         102 . The construction of  claim 101  wherein the first crystalline material is polycrystalline.  
     
     
         103 . The construction of  claim 101  wherein the first crystalline material is monocrystalline.  
     
     
         104 . The construction of  claim 88  wherein the second active regions are entirely contained within a single crystal of the second crystalline material.  
     
     
         105 . The construction of  claim 104  wherein the second crystalline material is polycrystalline.  
     
     
         106 . The construction of  claim 104  wherein the second crystalline material is monocrystalline.  
     
     
         107 . The construction of  claim 88  wherein: 
 the first transistor devices have gates over the first crystalline material;    the first crystalline material has a relaxed crystalline lattice; and    a strained crystalline lattice layer is between the relaxed crystalline lattice and the gates.    
     
     
         108 . The construction of  claim 107  wherein the strained crystalline lattice includes silicon.  
     
     
         109 . The construction of  claim 107  wherein the strained crystalline lattice includes silicon and germanium.  
     
     
         110 . The construction of  claim 88  wherein: 
 the second transistor devices have gates over the second crystalline material;    the second crystalline material has a relaxed crystalline lattice; and    a strained crystalline lattice layer is between the relaxed crystalline lattice and the gates.    
     
     
         111 . The construction of  claim 110  wherein the strained crystalline lattice includes silicon.  
     
     
         112 . The construction of  claim 110  wherein the strained crystalline lattice includes silicon and germanium.  
     
     
         113 . An integrated circuit, comprising: 
 a first crystalline material which includes silicon and germanium;    a pair of first transistor devices having first active regions extending into the first crystalline material, the active regions of the first transistor devices overlapping so that the pair of first transistor devices have a common source/drain region; the active regions of the pair of first transistor devices being entirely contained within a single crystal of the first crystalline material;    a second crystalline material which includes silicon and germanium, and which is electrically coupled with the common source/drain region; and    a pair of second transistor devices having second active regions extending into the second crystalline material.    
     
     
         114 . The circuit of  claim 113  wherein the first transistor devices are PFET devices and wherein the second transistor devices are NFET devices.  
     
     
         115 . The circuit of  claim 113  wherein the first transistor devices are NFET devices and wherein the second transistor devices are PFET devices.  
     
     
         116 . The circuit of  claim 113  wherein the first crystalline material comprises from about 10 to about 60 atomic percent germanium.  
     
     
         117 . The circuit of  claim 113  wherein the second crystalline material comprises from about 10 to about 60 atomic percent germanium.  
     
     
         118 . The circuit of  claim 113  wherein the second active regions overlap so that the second transistor devices have a shared source/drain region; and wherein the second active regions are entirely contained within a single crystal of the second crystalline material.  
     
     
         119 . The circuit of  claim 113  wherein: 
 the first transistor devices have gates over the first crystalline material;    the first crystalline material has a relaxed crystalline lattice; and    a strained crystalline lattice layer is between the relaxed crystalline lattice and the gates.    
     
     
         120 . The circuit of  claim 113  wherein: 
 the second transistor devices have gates over the second crystalline material;    the second crystalline material has a relaxed crystalline lattice; and    a strained crystalline lattice layer is between the relaxed crystalline lattice and the gates.    
     
     
         121 . An integrated circuit, comprising: 
 a first crystalline material which includes silicon and germanium;    a pair of first transistor devices having first active regions extending into the first crystalline material, the active regions of the first transistor devices overlapping so that the pair of first transistor devices have a common source/drain region;    a conductive interconnect electrically coupling the common source/drain region with a second crystalline material which includes silicon and germanium; and    a pair of second transistor devices having second active regions extending into the second crystalline material; the active regions of the pair of first transistor devices overlapping and being entirely contained within a single crystal of the second crystalline material.    
     
     
         122 . The circuit of  claim 121  wherein the first transistor devices are PFET devices and wherein the second transistor devices are NFET devices.  
     
     
         123 . The circuit of  claim 121  wherein the first transistor devices are NFET devices and wherein the second transistor devices are PFET devices.  
     
     
         124 . The circuit of  claim 121  wherein the first crystalline material comprises from about  10  to about  60  atomic percent germanium.  
     
     
         125 . The circuit of  claim 121  wherein the second crystalline material comprises from about  10  to about  60  atomic percent germanium.  
     
     
         126 . The circuit of  claim 121  wherein the second crystalline material is polycrystalline.  
     
     
         127 . The circuit of  claim 121  wherein the second crystalline material is monocrystalline.  
     
     
         128 . The circuit of  claim 121  wherein: 
 the first transistor devices have gates over the first crystalline material;    the first crystalline material has a relaxed crystalline lattice; and    a strained crystalline lattice layer is between the relaxed crystalline lattice and the gates.    
     
     
         129 . The circuit of  claim 121  wherein: 
 the second transistor devices have gates over the second crystalline material;    the second crystalline material has a relaxed crystalline lattice; and    a strained crystalline lattice layer is between the relaxed crystalline lattice and the gates.