Placement method for decoupling capacitors

Abstract

A method for placing decoupling capacitors in an integrated circuit during placement and routing stage. In the placement method, a floor plan of the integrated circuit is created, and includes the relative locations of a plurality of functional units. A power mesh comprising a plurality power lines is then overlaid on the floor plan, and the floor plan is divided into a plurality of windows. A plurality of semiconductor cells are placed into a portion of the windows. It is then determined whether a residual area comprising two adjacent windows without functional units and semiconductor cells disposed therein and at least three parallel power lines running theretrough exists. A MOS capacitor is then placed in the detected residual area, serving as a decoupling capacitor.

1 - 12 . (canceled)  
   
   
       13 . A semiconductor structure, comprising: 
 a substrate having a plurality of functional units and a plurality of semiconductor cells disposed therein;    a power mesh disposed on the substrate, comprising a plurality of first power lines and a plurality of second power lines, wherein the first and second power lines are arranged alternately; and    a MOS capacitor disposed in the substrate, having a gate connected to one of the first power lines, and a drain and a source respectively connected to the second power lines adjacent to the first power line connected to the gate.    
   
   
       14 . The semiconductor structure as claimed in  claim 13 , wherein the semiconductor structure is an application specific integrated circuit (ASIC).  
   
   
       15 . The semiconductor structure as claimed in  claim 13 , wherein the semiconductor structure is a microprocessor.  
   
   
       16 . The semiconductor structure as claimed in  claim 13 , wherein the first power lines are coupled to a power voltage (VCC) and the second power lines are coupled to ground.  
   
   
       17 . The semiconductor structure as claimed in  claim 16 , wherein the MOS capacitor is an NMOS transistor.  
   
   
       18 . The semiconductor structure as claimed in  claim 13 , wherein the first power lines are coupled to ground and the second power lines are coupled to a power voltage (VCC).  
   
   
       19 . The semiconductor structure as claimed in  claim 18 , wherein the MOS capacitor is a PMOS transistor.