Flat panel display device and fabrication method thereof

Abstract

A top-emitting organic light-emitting device can prevent a voltage drop by electrically coupling a cathode bus line to a cathode electrode. A method for fabricating the same is also disclosed. The flat panel display device comprises an insulating substrate having a pixel region and a non-pixel region, a first electrode arranged in the pixel region. a second electrode arranged in the pixel region and the non-pixel region, an organic emission layer and a charge transporting layer formed between the first electrode and the second electrode of the pixel region, and an electrode line formed in the pixel region and the non-pixel region. The electrode line and the second electrode are electrically and directly coupled to each other in the non-pixel region.

1 - 24 . (canceled)  
     
     
         25 . A flat panel display, comprising: 
 a substrate having an emission region and a non-emission region;    a plurality of thin film transistors arranged on the substrate;    a passivation layer arranged on the thin film transistors;    a first conductive line arranged at the emission region;    a second conductive line on the substrate;    an organic emission layer and a charge transporting layer arranged between the first conductive line and the second conductive line; and    a plurality of third conductive lines arranged on a portion of the non-emission region,    wherein the third conductive line and the second conductive line are electrically coupled with each other at the non-emission region.    
     
     
         26 . The flat panel display device of  claim 25 , wherein the third conductive line arranged in the portion of the non-emission region is a conductive material that absorbs an external light.  
     
     
         27 . The flat panel display device of  claim 26 , wherein the charge transporting layer is arranged between the third conductive line and the second conductive line.  
     
     
         28 . The flat panel display device of  claim 25 , wherein the third conducive line is a stripe like shape or a matrix like shape having an open portion that corresponds to the emission region.  
     
     
         29 . The flat panel display device of  claim 25 , wherein the charge transporting layer is arranged on the non-emission region and on the emission region.  
     
     
         30 . The flat panel display device of  claim 25 , wherein the third conductive line has a current with a voltage having a same polarity as the second conductive line.  
     
     
         31 . The flat panel display device of  claim 25 , wherein the third conductive line is a supplementary conductive line of the second conductive line.  
     
     
         32 . The flat panel display device of  claim 25 , wherein the third conductive line is directly coupled to the second conductive line.  
     
     
         33 . The flat panel display device of  claim 25 , wherein the third conductive line is arranged along a peripheral area of the non-emission region on the substrate so that the third conductive line is electrically coupled with the second conductive line.  
     
     
         34 . The flat panel display device of  claim 33 , wherein the third conductive line is directly coupled to the second conductive line.  
     
     
         35 . The flat panel display device of  claim 25 , wherein the third conductive line is arranged in at least one outer side of the non-emission region so that the third conductive line is electrically coupled with the second conductive line.  
     
     
         36 . The flat panel display device of  claim 35 , wherein the third conductive line is directly coupled to the second conductive line.  
     
     
         37 . The flat panel display device of  claim 25 , wherein the organic emission layer is only arranged on the first conductive line, and wherein the charge transporting layer is arranged on the non-emission region and on the emission region.  
     
     
         38 . The flat panel display device of  claim 25 , wherein a pixel defining layer is formed under at least one of the third conductive layers.  
     
     
         39 . The flat panel display device of  claim 25 , wherein the third conductive line is directly coupled to the second conductive line.  
     
     
         40 . A method for fabricating a flat panel display, comprising: 
 providing a substrate having an emission region and a non-emission region;    forming a plurality of thin film transistors on the substrate;    forming a passivation layer over the substrate on the thin film transistors;    forming a first conductive line on the emission region;    forming an organic emission layer and a charge transporting layer on the first conductive line;    forming a plurality of third conductive lines on the non-emission region; and    forming a second conductive line in the emission region and in the non-emission region,    wherein the third conductive line and the second conductive line are electrically coupled in the non-emission region.    
     
     
         41 . The method of  claim 40 , further comprising: 
 using a fine metal mask to partially form the organic emission layer on only the first conductive; and    using an open mask to form the charge transporting layer on the non-emission region.    
     
     
         42 . The method of  claim 40 , wherein the third conductive line is formed in a portion of the non-emission region.  
     
     
         43 . The method of  claim 40 , wherein the third conductive line arranged in the portion of the non-emission region is a conductive material that absorbs an external light.  
     
     
         44 . The method of  claim 43 , wherein the charge transporting layer is formed between a portion of the third conductive line, which is formed in the portion of the non-emission region, and the second electrode.  
     
     
         45 . The method of  claim 40 , wherein the third conductive line is directly coupled to the second conductive line.  
     
     
         46 . The method of  claim 40 , wherein the third conductive line is arranged in at least one outer side of the non-pixel region on the substrate to be electrically coupled with the second conductive line.  
     
     
         47 . The method of  claim 46 , wherein the third conductive line is directly coupled to the second conductive line.  
     
     
         48 . The method of  claim 40 , wherein the third conducive line is a stripe like shape or a matrix like shape having an open portion in the third conductive line that corresponds to the emission region.  
     
     
         49 . The method of  claim 40 , wherein the charge transporting layer is arranged on the non-emission region and on the emission region.  
     
     
         50 . The method of  claim 40 , wherein the third conductive line has a current with a voltage having a same polarity as the second conductive line.  
     
     
         51 . The method of  claim 40 , wherein the third conductive line is a supplementary conductive line of the second conductive line.  
     
     
         52 . The method of  claim 40 , wherein the third conductive line is arranged along an outer periphery of the non-emission region so that the third conductive line is electrically coupled with the second conductive line in the non-emission region.  
     
     
         53 . The method of  claim 52 , wherein the third conductive line is directly coupled to the second conductive line.  
     
     
         54 . The method of  claim 40 , wherein the third conductive line is arranged in at least one outer side of the non-emission region so that the third conductive line is electrically coupled with the second conductive line.  
     
     
         55 . The method of  claim 54 , wherein the third conductive line is directly coupled to the second conductive line.  
     
     
         56 . The method of  claim 40 , further comprising forming a pixel defining layer before forming the third conductive lines on the non-emission region.