Semiconductor device

Abstract

A functional block has a normal operation mode and a test mode. An external signal terminal receives an operation inhibition signal which is activated to inhibit the normal operation of the functional block. An external clock terminal receives an external clock. A test mode control circuit shifts the functional block from the normal operation mode to the test mode while the operation inhibition signal is in an activated state and the test mode control circuit is receiving the external clock. Accordingly, the semiconductor testing apparatus inputs the operation inhibition signal in a fixed activated state to the external signal terminal and inputs the external clock to the external clock terminal, thereby shifting the functional block to the test mode.

1 . A semiconductor device comprising: 
 a functional block having a normal operation mode and a test mode;    an external signal terminal receiving an operation inhibition signal which is activated to inhibit the normal operation of said functional block;    an external clock terminal receiving an external clock; and    a test mode control circuit that shifts said functional block from the normal operation mode to the test mode while the operation inhibition signal is in an activated state and the test mode control circuit is receiving the external clock.    
   
   
       2 . The semiconductor device according to  claim 1  wherein said test mode control circuit comprises: 
 a holding circuit that holds in advance flag information, and outputs the flag information while said test mode control circuit is receiving the external clock, the flag information indicating permission/inhibition for said functional block to shift from the normal operation mode to the test mode; and    a control circuit that activates a test mode signal when the operation inhibition signal is in an active state and the flag information from said holding circuit indicates permission, wherein    said functional block shifts from the normal operation mode to the test mode in response to activation of the test mode signal.    
   
   
       3 . The semiconductor device according to claim,  2  wherein 
 the flag information held in said holding circuit is rewritable.    
   
   
       4 . The semiconductor device according to  claim 2 , wherein: 
 said functional block is a memory block having nonvolatile memory cells;    to hold the flag information, said holding circuit comprises memory cells that are identical to those of the memory block.    
   
   
       5 . A semiconductor device comprising: 
 a functional block having a normal operation mode and a test mode;    an external clock terminal receiving an external clock whose duty ratio is variable;    a delay circuit that outputs a delayed clock which is generated by delaying the external clock;    an instruction code generator that sequentially receives a level of the external clock in synchronization with a transition edge of the delayed clock and outputs it as an instruction code; and    a test mode control circuit that shifts said functional block from the normal operation mode to the test mode when the instruction code indicates the test mode.    
   
   
       6 . The semiconductor device according to  claim 5 , wherein said test mode control circuit comprises: 
 a holding circuit that holds in advance a code indicating the test mode and outputs the code; and    a control circuit that activates a test mode signal in response to a coincidence of the instruction code and the code from said holding circuit, wherein    said functional block shifts from the normal operation mode to the test mode in response to activation of the test mode signal.    
   
   
       7 . The semiconductor device according to  claim 6 , wherein 
 the code held in said holding circuit is rewritable.    
   
   
       8 . The semiconductor device according to  claim 6 , wherein: 
 said functional block is a memory block having nonvolatile memory cells; and    to hold the code, said holding circuit comprises memory cells that are identical to those of the memory block.    
   
   
       9 . The semiconductor device according to  claim 5 , wherein: 
 said functional block has a plurality of test modes; and    when the instruction code indicates any of the plurality of test modes, said test mode control circuit shifts said functional block from the normal operation mode to the indicated test mode.    
   
   
       10 . The semiconductor device according to  claim 9 , wherein said test mode control circuit comprises: 
 a holding circuit that holds in advance a plurality of codes for output, the plurality of codes corresponding to the plurality of test modes; and    a control circuit that activates, in response to a coincidence of the instruction code and any of the plurality of codes from said holding circuit, one of the plurality of test mode signals corresponding to the coinciding code, wherein    in response to activation of any of the plurality of test mode signals, said functional block shifts from the normal operation mode to a test mode that corresponds to the activated test mode signal.    
   
   
       11 . The semiconductor device according to  claim 10 , wherein 
 the code held in said holding circuit is rewritable.    
   
   
       12 . The semiconductor device according to  claim 10 , wherein: 
 said functional block is a memory block having nonvolatile memory cells; and    to hold the code, said holding circuit comprises memory cells that are identical to those of the memory block.    
   
   
       13 . The semiconductor device according to  claim 5 , wherein 
 said test mode control circuit is possible to perform the test-mode control operation on said functional block when the instruction code indicates permission to the test mode, and shifts said functional block from the normal operation mode to the test mode when a subsequent instruction code indicates the test mode.