Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation

Abstract

A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.

1 . An electrostatic discharge protection device coupled to a pad of an internal circuit comprising: 
 a substrate;    a gate formed on the substrate;    a source and drain region formed in the substrate and respectively on both sides of the gate, the drain region being coupled to the pad and the source region being coupled to receive a reference voltage; and    a lightly doped region formed in the substrate, and only between the gate and the drain region, having a depth greater than that of the drain region,    wherein the projection of the gate does not overlap the lightly doped region.    
   
   
       2 . The electrostatic discharge protection device as claimed in  claim 1 , wherein the source and drain region are N +  doped regions.  
   
   
       3 . The electrostatic discharge protection device as claimed in  claim 1 , wherein the source and drain region are P +  doped regions.  
   
   
       4 . The electrostatic discharge protection device as claimed in  claim 1 , wherein the lightly doped region is an N −  type region.  
   
   
       5 . The electrostatic discharge protection device as claimed in  claim 1 , wherein the lightly doped region is a P −  type region.