Hybrid switching architecture

Abstract

A hybrid switching module includes a hybrid switching module processor data channel; a hybrid switching module main data channel; an input/output link data channel; a switch coupled to the hybrid switching module processor data channel; and a bridge coupled to the hybrid switching module main data channel; wherein the switch selectively coupled to the bridge and selectively coupled to the input/output link data channel, wherein the hybrid switching module processor data channel is thereby selectively coupled to the bridge and selectively coupled to the input/output link data channel.

1 . A system comprising: 
 a first processor including a first processor data channel;    a first hybrid switching module including a first hybrid switching module processor data channel, a first hybrid switching module main data channel, and a first input/output link data channel, the first hybrid switching module processor data channel being coupled to the first processor data channel;    a first main bus coupled to the first hybrid switching module main data channel allowing the first processor to access a first peripheral device coupled with the first main bus to implement a first function;    a second processor including a second processor data channel;    a second hybrid switching module including a second hybrid switching module processor data channel, a second hybrid switching module main data channel, and a second input/output link data channel, the second hybrid switching module processor data channel being coupled to the second processor data channel, the second input/output link data channel being coupled to the first input/output link data channel; and    a second main bus coupled to the second hybrid switching module main data channel allowing the second processor to access a second peripheral device coupled with the second main bus to implement a second function that is not redundant to the first function; 
 wherein the first hybrid switching module selectively couples the first input/output link data channel with the first main bus allowing the second processor to access the first peripheral device on the first main bus to implement the first function, and the second hybrid switching module selectively couples the second input/output link data channel with the second main bus allowing the first processor to access the second peripheral device on the second main bus to implement the second non-redundant function.  
   
   
   
       2 . The system of  claim 1  further comprising: 
 a third processor including a third processor data channel; and    a third hybrid switching module including a third hybrid switching module processor data channel, a third input/output link data channel, and a fourth input/output link data channel, the third hybrid switching module processor data channel being coupled to the third processor data channel;    wherein said first hybrid switching module further comprises a fifth input/output link data channel;    wherein the third input/output link data channel is coupled to the fifth input/output link data channel;    wherein said second hybrid switching module further comprises a sixth input/output link data channel;    wherein the fourth input/output link data channel is coupled to the sixth input/output link data channel.    
   
   
       3 . The system of  claim 2  wherein said third hybrid switching module further comprises a third hybrid switching module main data channel, wherein said system further comprises: 
 a third main bus coupled to the second hybrid switching module main data channel.    
   
   
       4 . The system of  claim 3  wherein the third main bus allows the third processor to access a third peripheral device coupled with the third main bus to implement a third function that is not redundant to the first function and the second function.  
   
   
       5 . The system of  claim 1  wherein upon a failure mode, the first hybrid switching module selectively couples the first input/output link data channel with the first main bus allowing the second processor to access the first peripheral device on the first main bus to implement the first function, and wherein upon a failure mode the second hybrid switching module selectively couples the second input/output link data channel with the second main bus allowing the first processor to access the second peripheral device on the second main bus to implement the second non-redundant function.  
   
   
       6 . A method comprising: 
 accessing, from a first processor, a first peripheral device coupled to a first main bus, wherein the first processor is coupled to the first main bus through a first hybrid switching module;    implementing a first function at the first peripheral device;    accessing, from the first processor, a second peripheral device coupled to a second main bus, wherein the first processor is selectively coupled to the second main bus through the first hybrid switching module and a second hybrid switching module, the first hybrid switching module coupled to the second hybrid switching module through a first input/output link data channel being and a second input/output link data channel; and    implementing a second function at the second peripheral device, the second function being non-redundant to the first function.    
   
   
       7 . The method of  claim 6  further comprising: 
 accessing, from a second processor, the second peripheral device coupled to the second main bus, wherein the second processor is coupled to the first main bus through a first hybrid switching module; and    implementing the second function at the first peripheral device.    
   
   
       8 . The method of  claim 7  further comprising: 
 accessing, from the second processor, the first peripheral device coupled to the first main bus, wherein the second processor is selectively coupled to the first main bus through the first hybrid switching module and the second hybrid switching module; and    implementing the first function at the second peripheral device.    
   
   
       9 . The method of  claim 8  further comprising accessing, from the second processor, the first peripheral device coupled to the first main bus upon a failure.  
   
   
       10 . The method of  claim 6  further comprising accessing, from the first processor, the second peripheral device coupled to the first main bus upon a failure.  
   
   
       11 . A method comprising: 
 coupling a first processor to a first main bus through a first hybrid switching module;    coupling a first peripheral device to the first main bus, the first peripheral device implementing a first function;    coupling a second processor to a second main bus through a second hybrid switching module;    coupling a second peripheral device to the second main bus, the second peripheral device implementing a second function that is not redundant to the first function; and    coupling the first hybrid switching module to the second hybrid switching module through an input/output link.    
   
   
       12 . The method of  claim 11  further comprising sending data from the first processor to the second peripheral device, wherein the data is sent through the first hybrid switching module, the second hybrid switching module and the input/output link.  
   
   
       13 . The method of  claim 12  further comprising sending data from the first processor to the second peripheral device upon detection of a failure.  
   
   
       14 . A method comprising: 
 sending data communications from a first processor to a first peripheral device coupled to a first main bus, the first processor coupled to the first main bus through a first hybrid switching module;    sending data communications from a second processor to a second peripheral device coupled to a second main bus, the second processor coupled to the second main bus through a second hybrid switching module;    detecting a failure of the second processor; and    sending data communications from the first processor to the second peripheral device coupled to the second main bus, the first processor coupled selectively coupled to the second main bus through the first hybrid switching module and the second hybrid switching module.    
   
   
       15 . The method of  claim 14  further comprising coupling the first hybrid switching module to the second hybrid switching module through an input/output link.  
   
   
       16 . The method of  claim 14  further comprising implementing a first function at the first peripheral device upon receipt of the data communications from the first processor.  
   
   
       17 . The method of  claim 16  further comprising implementing a second function at the second peripheral device upon receipt of the data communications from the first processor, wherein the second function is not redundant to the first function.