Flash memory structure and fabrication method thereof

Abstract

A flash memory structure comprises a semiconductor substrate, a source region, a drain region, a first insulating dielectric layer, a floating gate, a second insulating dielectric layer, and a control gate. The semiconductor substrate has a first top surface and a second top surface that is lower than the first top surface. The source region and the drain region are respectively in the second top surface and the first top surface of the semiconductor substrate, and the semiconductor substrate connecting the source region and the drain region is a vertical channel region. The whole channel region is covered by the first insulating dielectric layer, the floating gate, the second insulating dielectric layer, and the control gate in turn.

1 . A flash memory structure, comprising: 
 a semiconductor substrate having at least a first top surface and at least a second top surface, wherein the first top surface is higher than the second top surface;    a source region formed in the second top surface of the semiconductor substrate;    a drain region formed in the first top surface of the semiconductor substrate, wherein the semiconductor substrate connecting the source region and the drain region is a vertical channel region;    a first insulating dielectric layer conformally formed on the vertical channel region to cover the vertical channel region;    a floating gate covering the first insulating dielectric layer;    a second insulating dielectric layer covering the floating gate; and    a control gate covering the second insulating dielectric layer.    
   
   
       2 . The flash memory structure of  claim 1 , wherein the floating gate is selected from a group consisting of a polysilicon layer and a silicon nitride layer.  
   
   
       3 . The flash memory structure of  claim 1 , wherein the vertical channel region between the source region and the drain region comprises an L-shaped three-dimensional structure.  
   
   
       4 . The flash memory structure of  claim 1 , wherein the first insulating dielectric layer comprises a tunneling oxide layer.  
   
   
       5 . The flash memory structure of  claim 1 , wherein the floating gate surrounds three side surfaces of the vertical channel region.  
   
   
       6 . The flash memory structure of  claim 5 , wherein the floating gate further covers a top surface of the vertical channel.  
   
   
       7 . The flash memory structure of  claim 1 , wherein the control gate comprises a polysilicon layer.  
   
   
       8 . A method of fabricating a flash memory structure, comprising the steps of: 
 patterning a semiconductor substrate to remove part of the semiconductor substrate to a predetermined depth with a plurality of island blocks formed in the semiconductor substrate and a trench formed between two adjacent island blocks, wherein a top surface of each of the island blocks is a first top surface of the semiconductor substrate and a surface of the trench is a second top surface of the semiconductor substrate;    forming a first insulating dielectric layer on the semiconductor substrate to simultaneously cover the island blocks and the trench;    forming a charge storage layer pattern on the first insulating dielectric layer such that the trench is filled with the charge storage layer pattern;    forming a second insulating dielectric layer on the charge storage layer pattern to cover the charge storage layer pattern;    forming a conductive layer on the second insulating dielectric layer to cover the second insulating dielectric layer;    patterning the conductive layer, the second insulating dielectric layer and the charge storage layer pattern to form a gate stack unit such that part of the first insulating dielectric layer in the trench and part of the first insulating dielectric layer on the island block are exposed, wherein the gate stack unit covers at least part of the three side surfaces of the island block, and is positioned on part of the trench and part of the island block; and    implanting ions into part of the first top surface and the second top surface of the semiconductor substrate to form respectively a drain region and a source region.    
   
   
       9 . The method of  claim 8 , wherein the first insulating dielectric layer comprises a tunneling oxide layer.  
   
   
       10 . The method of  claim 8 , wherein the conductive layer comprises a polysilicon layer.  
   
   
       11 . The method of  claim 8 , wherein the charge storage layer pattern is a polysilicon layer or a silicon nitride layer.  
   
   
       12 . The method of  claim 8 , wherein the charge storage layer pattern is used as a floating gate and the conductive layer is used as a control gate.  
   
   
       13 . The method of  claim 8 , further comprising a step of forming a nitride covering layer on the conductive layer after the conductive layer is formed, and before the step of patterning the conductive layer, the second insulating dielectric layer and the charge storage layer pattern.  
   
   
       14 . The method of  claim 8 , further comprising a step of forming a sidewall spacer on one side of the gate stack unit before the step of implanting the ions.  
   
   
       15 . The method of  claim 8 , wherein the semiconductor substrate connecting the source region and the drain region comprises a vertical channel region.  
   
   
       16 . The method of  claim 15 , wherein the vertical channel region comprises an L-shaped three-dimensional structure.  
   
   
       17 . The method of  claim 15 , wherein the gate stack unit formed from the conductive layer, the second insulating dielectric layer and the charge storage layer pattern completely covers the vertical channel path.  
   
   
       18 . A flash memory structure with a vertical channel region, comprising: 
 a semiconductor substrate having at least a first top surface and at least a second top surface, wherein the first top surface is the top surface of an island block in the semiconductor substrate and the second top surface is the surface of a trench in the semiconductor substrate, and the first top surface is higher than the second top surface;    a source region disposed in the second top surface of the semiconductor substrate;    a drain region disposed in the first top surface of the semiconductor substrate, wherein the semiconductor substrate connecting the source region and the drain region is a vertical channel region comprising a sidewall of the island block;    a first insulating dielectric layer formed on the vertical channel region to completely cover the vertical channel region;    a floating gate covering the first insulating dielectric layer to a extent of surrounding three side surfaces of the vertical channel region;    a second insulating dielectric layer covering the floating gate; and    a control gate covering the second insulating dielectric layer.    
   
   
       19 . The flash memory structure of  claim 18 , wherein the vertical channel region connecting the source region and the drain region comprises an L-shaped three-dimensional structure.  
   
   
       20 . The flash memory structure of  claim 18 , further comprising: 
 a nitride covering layer formed on the control gate; and    two sidewall spacers on both sides of a gate stack unit comprising the floating gate, the second insulating dielectric layer and the control gate.