Electronic devices having partially elevated source/drain structures and related methods

Abstract

Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode. An insulating layer may be formed on the semiconductor substrate including the first and second impurity doped regions, and first and second holes may be formed in the insulating layer, with the first and second holes respectively exposing portions of the first and second impurity doped regions. In addition, first and second epitaxial semiconductor layers may be formed in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate. Related devices are also discussed.

1 . A method of forming an electronic device, the method comprising: 
 forming a gate electrode on a semiconductor substrate;    forming first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode;    forming an insulating layer on the semiconductor substrate including the first and second impurity doped regions;    forming first and second holes in the insulating layer, the first and second holes respectively exposing portions of the first and second impurity doped regions; and    forming first and second epitaxial semiconductor layers in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate.    
   
   
       2 . A method according to  claim 1  wherein a crystal structure of the first and second epitaxial semiconductor layers is aligned with respect to a crystal structure of the semiconductor substrate.  
   
   
       3 . A method according to  claim 1  wherein forming the insulating layer comprises forming the insulating layer on the gate electrode such that the gate electrode is between the insulating layer and the semiconductor substrate.  
   
   
       4 . A method according to  claim 1  wherein the first and second impurity doped regions of the semiconductor substrate have impurity concentrations that are less than impurity concentrations of at least portions of the respective first and second epitaxial semiconductor layers.  
   
   
       5 . A method according to  claim 1  further comprising: 
 after forming the first and second epitaxial semiconductor layers, forming first and second conductive plugs in the respective first and second holes on the respective first and second epitaxial semiconductor layers.    
   
   
       6 . A method according to  claim 5  wherein each of the first and second conductive plugs comprises doped polysilicon.  
   
   
       7 . A method according to  claim 5  wherein each of the first and second conductive plugs comprises a metal.  
   
   
       8 . A method according to  claim 7  wherein the first and second conductive plugs are in ohmic contact with the respective first and second epitaxial semiconductor layers.  
   
   
       9 . A method according to  claim 1  further comprising: 
 before forming the insulating layer, forming sidewall spacers on sidewalls of the gate electrode such that a sidewall spacer and portions of the insulating layer are between the gate electrode and each of the first and second epitaxial semiconductor layers.    
   
   
       10 . A method according to  claim 1  wherein an impurity dopant concentration of each of the first and second epitaxial semiconductor layers increases with increasing distance from the semiconductor substrate.  
   
   
       11 . A method according to  claim 1  further comprising: 
 forming a gate insulating layer such that the gate insulating layer is between the gate electrode and the semiconductor substrate.    
   
   
       12 . An electronic device comprising: 
 a semiconductor substrate;    a gate electrode on the semiconductor substrate;    first and second impurity doped regions of the semiconductor substrate on opposite sides of the gate electrode;    an insulating layer on the semiconductor substrate including the first and second impurity doped regions, the insulating layer having first and second holes therein respectively exposing portions of the first and second impurity doped regions; and    first and second epitaxial semiconductor layers in the respective first and second holes on the exposed portions of the first and second impurity doped regions of the semiconductor substrate.    
   
   
       13 . An electronic device according to  claim 12  wherein the insulating layer is on the gate electrode such that the gate electrode is between the insulating layer and the semiconductor substrate.  
   
   
       14 . An electronic device according to  claim 12  wherein the first and second impurity doped regions of the semiconductor substrate have impurity concentrations that are less than impurity concentrations of at least portions of the respective first and second epitaxial semiconductor layers.  
   
   
       15 . An electronic device according to  claim 12  further comprising: 
 first and second conductive plugs in the respective first and second holes such that the first and second epitaxial semiconductor layers are between the respective first and second conductive plugs and the first and second impurity doped regions of the semiconductor substrate.    
   
   
       16 . An electronic device according to  claim 15  wherein each of the first and second conductive plugs comprises doped polysilicon.  
   
   
       17 . An electronic device according to  claim 15  wherein each of the first and second conductive plugs comprises a metal.  
   
   
       18 . An electronic device according to  claim 17  wherein the first and second conductive plugs are in ohmic contact with the respective first and second epitaxial semiconductor layers.  
   
   
       19 . An electronic device according to  claim 12  further comprising: 
 sidewall spacers on sidewalls of the gate electrode such that a sidewall spacer and portions of the insulating layer are between the gate electrode and each of the first and second epitaxial semiconductor layers.    
   
   
       20 . An electronic device according to  claim 12  wherein an impurity dopant concentration of each of the first and second epitaxial semiconductor layers increases with increasing distance from the semiconductor substrate.  
   
   
       21 . An electronic device according to  claim 12  further comprising: 
 a gate insulating layer between the gate electrode and the semiconductor substrate.    
   
   
       22 - 38 . (canceled)