Semiconductor device having dual-STI and manufacturing method thereof

Abstract

A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.

1 . A semiconductor device having a first area and a second area, comprising: 
 a silicon substrate; and    an isolation structure implemented by a silicon insulating film formed on a surface of said silicon substrate; wherein    a depth of said isolation structure in said first area is smaller than a depth of said isolation structure in said second area, and    an isolation height of said isolation structure in said first area is substantially equal to an isolation height of said isolation structure in said second area.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein 
 a trench width of said isolation structure in said first area is smaller than a trench width of said isolation structure in said second area.    
   
   
       3 . The semiconductor device according to  claim 1 , further comprising: 
 a first gate structure formed in an element area defined by said isolation structure in said first area;    a second gate structure formed in an element area defined by said isolation structure in said second area; and    a third gate structure formed astride said first area and said second area.    
   
   
       4 . The semiconductor device according to  claim 3 , wherein 
 said first gate structure includes a first gate insulating film formed over said silicon substrate, a lower electrode formed over said first gate insulating film and including a first conductive film, an insulating film formed over said lower electrode, and an upper electrode formed over said insulating film and including a second conductive film,    said second gate structure includes a second gate insulating film formed over said silicon substrate and a gate electrode formed over said second gate insulating film and including said second conductive film, and    said third gate structure includes said first conductive film and said insulating film formed in said first area and said second conductive film formed astride said first area and said second area so as to cover said first conductive film and said insulating film.    
   
   
       5 . The semiconductor device according to  claim 4 , wherein 
 a film thickness of said first gate insulating film is different from a film thickness of said second gate insulating film.    
   
   
       6 . The semiconductor device according to  claim 1 , wherein 
 a boundary between said first area and said second area is present in said isolation structure.    
   
   
       7 . A method of manufacturing a semiconductor device having a first area and a second area, comprising the steps of: 
 forming a first silicon insulating film over a silicon substrate;    forming a first trench in said first silicon insulating film and said silicon substrate in said first and said second areas;    forming a mask layer in said first trench formed in said first area and over said first silicon insulating film in said first area;    etching said silicon substrate using said mask layer and said first silicon insulating film as a mask, so as to form a second trench in said first trench in said second area;    removing said mask layer;    forming a second silicon insulating film over said first silicon insulating film so as to bury said first and said second trenches; and    removing said first and said second silicon insulating films over said silicon substrate so as to form an isolation structure in said first and said second trenches.    
   
   
       8 . The method of manufacturing a semiconductor device according to  claim 7 , further comprising the steps of: 
 forming a first gate insulating film over said silicon substrate in said first area;    forming a first conductive film over said first gate insulating film;    forming an insulating film over said first conductive film;    forming a second gate insulating film over said silicon substrate in said second area;    forming a second conductive film over said insulating film and said second gate insulating film;    etching said second conductive film to leave at least said second conductive film present at a boundary between said first area and said second area, so as to form an upper electrode on said insulating film in said first area, to form a gate electrode on said second gate insulating film in said second area, and to form said second conductive film implementing a gate structure at the boundary between said first area and said second area; and    etching said insulating film and said first conductive film, so as to form a lower electrode over said first gate insulating film and to form said insulating film and said first conductive film implementing the gate structure in said first area around said boundary.    
   
   
       9 . The method of manufacturing a semiconductor device according to  claim 7 , wherein 
 said step of forming a mask layer includes the step of forming said mask layer in a part of said first trench.    
   
   
       10 . The method of manufacturing a semiconductor device according to  claim 7 , further comprising the step of forming a silicon nitride film over said silicon substrate prior to the step of forming said first silicon insulating film.  
   
   
       11 . A semiconductor device having a first area and a second area, comprising: 
 a silicon substrate;    an isolation structure implemented by a silicon insulating film formed on a surface of said silicon substrate; wherein    a depth of said isolation structure in said first area is smaller than a depth of said isolation structure in said second area, and    a trench width of said isolation structure in said first area is smaller than a trench width of said isolation structure in said second area.