MOS electric fuse, its programming method, and semiconductor device using the same

Abstract

A programming method of a MOS electric fuse includes steps of preparing, as a fuse element, a MOS transistor which comprises second conductivity type first and second impurity regions formed to face with each other on an upper surface of a first conductivity type well on a semiconductor substrate, a gate dielectric film formed on the upper surface of the well at least between the first and second impurity regions, and a gate electrode formed through the gate dielectric film on the upper surface of the well between the first and second impurity regions and applying a first voltage to the gate electrode, and a second voltage different from the first voltage to the first impurity region, and short-circuiting the gate dielectric film only between the gate electrode and the first impurity region.

1 . A programming method of a MOS electric fuse comprising: 
 preparing, as a fuse element, a MOS transistor which comprises a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of a well of a first conductivity type on a semiconductor substrate, a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region, and a gate electrode formed through the gate dielectric film on the upper surface of the well held between the first impurity region and the second impurity region; and    applying a first voltage to the gate electrode, and a second voltage different from the first voltage to the first impurity region, and short-circuiting the gate dielectric film only between the gate electrode and the first impurity region.    
   
   
       2 . The method according to  claim 1 , wherein the first voltage and the second voltage form no channels between the first impurity region and the second impurity region.  
   
   
       3 . The method according to  claim 1 , wherein the first conductivity type is an n type, and the MOS transistor is a PMOS transistor.  
   
   
       4 . The method according to  claim 3 , wherein the first voltage is a positive potential, and the second voltage is a ground potential.  
   
   
       5 . The method according to  claim 1 , wherein the first conductivity type is a p type, and the MOS transistor is an NMOS transistor.  
   
   
       6 . The method according to  claim 5 , wherein the first voltage is a ground potential, and the second voltage is a positive potential.  
   
   
       7 . The method according to  claim 1 , further comprising applying a third voltage to the gate electrode, and a fourth voltage different from the third voltage to the second impurity region, and short-circuiting a portion only between the gate electrode and the second impurity region.  
   
   
       8 . A programming method of a MOS electric fuse comprising: 
 preparing, as a fuse element, a MOS transistor which comprises a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of a well of a first conductivity type on a semiconductor substrate, a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region, and a gate electrode formed through the gate dielectric film on the upper surface of the well held between the first impurity region and the second impurity region; and    applying a first voltage to the gate electrode, and a second voltage different from the first voltage to the well, and substantially short-circuiting the gate dielectric film between the gate electrode and a surface of the well on a substantial center alone between the first impurity region and the second impurity region.    
   
   
       9 . The method according to  claim 8 , wherein the semiconductor well is an n type, and the MOS transistor is a PMOS transistor.  
   
   
       10 . The method according to  claim 9 , wherein the first voltage is a ground potential, and the second voltage is a positive potential.  
   
   
       11 . The method according to  claim 8 , wherein the semiconductor well is a p type, and the MOS transistor is an NMOS transistor.  
   
   
       12 . The method according to  claim 11 , wherein the first voltage is a positive potential, and the second voltage is a ground potential.  
   
   
       13 . A MOS electric fuse comprising: 
 a semiconductor substrate;    a well of a first conductivity type formed on an upper surface of the semiconductor substrate;    a first impurity region and a second impurity region of a second conductivity type formed to face with each other on an upper surface of the well;    a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region; and    a gate electrode formed through the gate dielectric film on the upper surface of the well between the first impurity region and the second impurity region,    wherein substantially binary states of conduction and nonconduction are independently set between the first impurity region and the gate electrode and between the second impurity region and the gate electrode.    
   
   
       14 . The MOS electric fuse according to  claim 13 , wherein the well is electrically connected to the gate electrode.  
   
   
       15 . A MOS electric fuse device comprising: 
 a semiconductor substrate;    a well of a first conductivity type formed on an upper surface of the semiconductor substrate;    a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of the well;    a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region; and    a gate electrode formed through the gate dielectric film on the upper surface of the well held between the first impurity region and the second impurity region,    wherein substantially binary states of conduction and nonconduction are set only between a substantial center between the first impurity region and the second impurity region and a portion of the gate electrode opposed to the center.    
   
   
       16 . The MOS electric fuse device according to  claim 15 , wherein the well is electrically connected to the first impurity region and the second impurity region.  
   
   
       17 . A semiconductor device comprising: 
 a semiconductor substrate;    a plurality of wells of a first conductivity type formed on an upper surface of the semiconductor substrate; and    a plurality of semiconductor structures formed in the plurality of wells, each of the plurality of semiconductor structures comprising 
 a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of each of the wells,  
 a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region and having portions covering the first impurity region and the second impurity region, and  
 a gate electrode formed through the gate dielectric film on the upper surface of the well held between the first impurity region and the second impurity region and having places opposed to the first impurity region and the second impurity region,  
   wherein, regarding a first opposed place of the first impurity region and the gate electrode, and a second opposed place of the second impurity region and the gate electrode, there are a first state in which the first opposed place and the second opposed place are both in insulated states, a second state in which the first opposed place only is substantially short-circuited, a third state in which the second opposed place only is substantially short-circuited, and    each of the plurality of semiconductor structures belongs to one of the first state to the third state.    
   
   
       18 . A semiconductor device comprising: 
 a semiconductor substrate;    a well of a first conductivity type formed on an upper surface of the semiconductor substrate;    a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of the well;    a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region;    a gate electrode formed through the gate dielectric film on the upper surface of the well held between the first impurity region and the second impurity region;    a first terminal connected to the first impurity region;    a second terminal connected to the second impurity region;    a third terminal connected to the gate electrode;    a fourth terminal connected to the well;    a first functional circuit connected to the first terminal; and    a second functional circuit connected to the second terminal,    wherein binary states of conduction and nonconduction are substantially set between the first terminal and the third terminal and between the second terminal and the third terminal.    
   
   
       19 . The semiconductor device according to  claim 18 , wherein the first functional circuit and the second functional circuit include sense amplifiers to read the binary states.  
   
   
       20 . The semiconductor device according to  claim 18 , wherein the first functional circuit and the second functional circuit include memory cells for a memory circuit.