Generation and measurement of timing delays by digital phase error compensation

Abstract

A circuit and method for generating a delayed event following a trigger pulse occurring at a random time between clock pulses is disclosed. The circuit includes a clock circuit, a voltage converter, an analog-to-digital converter circuit, a memory storage circuit, and a summing circuit. The method includes representing the time between the triggering pulse and a subsequent clock pulse as a voltage, converting the voltage to a stored digital value, and defining a desired delay time by adding a first time determined by counting a predetermined number of clock cycles to a second time determined by converting the stored digital value first to an analog value and then to a time value.

1 . A method for measuring a time between two trigger events, the method comprising 
 initiating a first ramp voltage for the duration of a time between a first trigger event and a subsequent clock pulse;    initiating a time counter contemporaneously with the end of the first ramp voltage;    initiating a second ramp voltage for the duration of a time between a second trigger event and a subsequent clock pulse;    terminating the time counter contemporaneously with the end of the second ramp voltage; and    calculating the delay between the first trigger event and the second trigger event.    
   
   
       2 . The method of claim  52 , further comprising converting a peak voltage of the first ramp voltage to a first time value and converting a peak voltage of the second ramp voltage to a second time value.  
   
   
       3 . The method of claim  52 , wherein calculating the delay between the first trigger event and the second trigger event comprises converting a peak voltage of the first ramp voltage to a first time value, converting a peak voltage of the second ramp voltage to a second time value, summing the first time value with the time counter, and subtracting the second time value from the time counter.  
   
   
       4 . A method for self-calibrating a delay measurement and generation circuit, the method comprising: 
 initiating a first voltage ramp for about one clock cycle;    storing a first peak voltage of the first voltage ramp;    initiating a second voltage ramp for about two clock cycles;    storing a second peak voltage of the second voltage ramp;    calculating the slope and intercept of a voltage-to-time line including the first and second peak voltages.    
   
   
       5 . The method of claim  55 , wherein storing a first peak voltage of the first voltage ramp comprises sampling and holding the voltage ramp after about one clock cycle.  
   
   
       6 . The method of claim  55 , wherein storing a second peak voltage of the second voltage ramp comprises sampling and holding the voltage ramp after about one clock cycle.  
   
   
       7 . The method of claim  55 , wherein storing a first peak voltage of the first voltage ramp comprises converting the first peak voltage to a first digital value and subsequently storing the first digital value in a memory location.  
   
   
       8 . The method of claim  55 , wherein storing a second peak voltage of the second voltage ramp comprises converting the second peak voltage to a second digital value and subsequently storing the second digital value in a memory location.  
   
   
       9 . The method of claim  55 , further comprising storing the slope and intercept of the voltage-to-time line in a memory location.