Method for improving the thermal stability of silicide

Abstract

An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer 110 . The method may include forming an interface layer 200 over the semiconductor substrate 20 and performing an anneal to create a silicide 190 on the top surface of the gate electrode 110.

1 . A method for making a transistor, comprising: 
 providing a semiconductor substrate;    forming a gate dielectric layer over said semiconductor substrate;    forming a gate electrode layer over said gate dielectric layer; and    performing an ion implant on said gate electrode layer.    
   
   
       2 . The method of  claim 1  further comprising: 
 etching said gate electrode layer and said gate dielectric layer to form a gate stack having a gate electrode and a gate dielectric;    forming extension sidewalls coupled to said gate stack;    implanting extension regions within a top surface of said semiconductor substrate;    forming source/drain sidewalls coupled to said extension sidewalls;    implanting source/drain regions within a top surface of said semiconductor substrate;    annealing said semiconductor substrate;    forming an interface layer over said semiconductor substrate; and    performing an anneal to create a silicide within a top surface of said gate electrode.    
   
   
       3 . The method of  claim 1  wherein said ion implant is a Ar + ion implant.  
   
   
       4 . The method of  claim 1  wherein said ion implant is a N 2   + ion implant.  
   
   
       5 . The method of  claim 1  wherein said ion implant is a F + ion implant.  
   
   
       6 . The method of  claim 1  wherein said ion implant is a Sb + ion implant.  
   
   
       7 . The method of  claim 1  wherein said gate electrode layer comprises polycrystalline silicon.  
   
   
       8 . The method of  claim 1  wherein said gate electrode layer comprises amorphous silicon.  
   
   
       9 . The method of  claim 1  wherein said transistor is a CMOS transistor.  
   
   
       10 . The method of  claim 1  wherein said transistor is a PMOS transistor.  
   
   
       11 . The method of  claim 1  wherein said transistor is a NMOS transistor.  
   
   
       12 . The method of  claim 2  wherein said anneal to create a silicide is a rapid thermal anneal.  
   
   
       13 . The method of  claim 2  wherein said interface layer comprises Ni.  
   
   
       14 . The method of  claim 2  wherein said interface layer comprises Co.  
   
   
       15 . The method of  claim 2  wherein said silicide is a self-aligned silicide.  
   
   
       16 . A method for forming a silicide on a gate of a transistor, comprising: 
 providing a semiconductor substrate;    forming a gate dielectric layer over said semiconductor substrate;    forming a gate electrode layer over said gate dielectric layer, said gate electrode layer comprising polycrystalline silicon;    performing an Ar + ion implant on said gate electrode layer;    etching said gate electrode layer and said gate dielectric layer to form a gate stack having a gate electrode and a gate dielectric;    forming extension sidewalls coupled to said gate stack;    implanting extension regions within a top surface of said semiconductor substrate;    forming source/drain sidewalls coupled to said extension sidewalls;    implanting source/drain regions within a top surface of said semiconductor substrate;    annealing said semiconductor substrate to recrystallize a surface region of said gate electrode modified by said Ar + ion implant;    forming an interface layer over said semiconductor substrate, said interface layer including Ni; and    performing a rapid thermal anneal to create a nickel silicide within said surface region of said gate electrode.    
   
   
       17 . The method of  claim 16  further including the step of forming a cap layer over said interface layer prior to said step of performing a rapid thermal anneal.  
   
   
       18 . The method of  claim 16  further comprising: 
 performing a second rapid thermal anneal subsequent to said step of performing a rapid thermal anneal.    
   
   
       19 . A method for forming a silicide on a gate of a transistor, comprising: 
 providing a semiconductor substrate;    forming a gate dielectric layer over said semiconductor substrate;    forming a gate electrode layer over said gate dielectric layer;    etching said gate electrode layer and said gate dielectric layer to form a gate stack having a gate electrode and a gate dielectric;    forming extension sidewalls coupled to said gate stack;    implanting extension regions within a top surface of said semiconductor substrate;    forming source/drain sidewalls coupled to said extension sidewalls;    implanting source/drain regions within a top surface of said semiconductor substrate;    performing an Ar + ion implant;    annealing said semiconductor substrate;    forming an interface layer over said semiconductor substrate; and    performing an anneal to create a silicide on a top surface of said gate electrode.    
   
   
       20 . The method of  claim 19  wherein said gate electrode layer comprises polycrystalline silicon.  
   
   
       21 . The method of  claim 19  wherein said gate electrode layer comprises amorphous silicon.  
   
   
       22 . The method of  claim 19  wherein said transistor is a CMOS transistor.  
   
   
       23 . The method of  claim 19  wherein said transistor is a PMOS transistor.  
   
   
       24 . The method of  claim 19  wherein said transistor is a NMOS transistor.  
   
   
       25 . The method of  claim 19  wherein said anneal to create a silicide is a rapid thermal anneal.  
   
   
       26 . The method of  claim 19  wherein said interface layer comprises Ni.  
   
   
       27 . The method of  claim 19  wherein said interface layer comprises Co.  
   
   
       28 . The method of  claim 19  wherein said silicide is a self-aligned silicide.