Lateral PNP transistor and the method of manufacturing the same

Abstract

The present invention relates to a lateral PNP transistor and the method of manufacturing the same. The medium doping N-type base area and the light doping P − collector area were first introduced in the structure before the formation of P + doping emitter area and the collector area. The emitter-base-collector doping profile in the lateral and the base width of LPNP were similar to NPN. The designer can optimize the doping profile and area size of each area according to the request of the current gain (Hfe), collector-base breakdown voltage (BVceo), and Early voltage (VA) of LPNP transistor. These advantages may cause to reduce the area and enhance performance of the LPNP transistor.

1 . A Lateral PNP transistor, comprising: 
 A N-type buried layer, which is surrounded by a P-type buried layer, is formed on a surface of a P-type doping substrate; and    A N-type epi layer is formed on the surface of substrate, N-type buried layer, P-type buried layers; together with a deep N + -type sinker areas are formed on the top edge of buried layer and a N + -type base is formed on the top of the N + -sinker, characterizing that:    Based on the structure of P +  doping emitter and collector of enhancement LPNP transistor, carries on the medium doping N-type base and light doping P −  collector and surround the P +  doping emitter and collector respectively, that provides the emitter-base-collector doping profile in lateral and base width of LPNP to be equal to NPN transistor;    Finally, the metal electrode of collector, metal electrode of base, and the metal electrode of emitter are formed.    
   
   
       2 . The lateral PNP transistor structure of  claim 1 , wherein the doping profile and the size of the medium doping N-type base area and light doping P −  collector area can be determined according to the request of the current gain (Hfe), collector-base breakdown voltage (BVceo), and Early voltage (VA) of LPNP transistor.  
   
   
       3 . The lateral PNP transistor structure of  claim 1 , wherein an N-type field implant layer is formed on the N-type epi layer.  
   
   
       4 . The lateral PNP transistor structure of  claim 1 , wherein the deep N + -type sinker under the N + -type base could be surrounding type, one-side deep N + -type sinker, or no deep N + -type sinker.  
   
   
       5 . A manufacturing method of lateral PNP transistor, wherein a N-type buried layer (Buried N) is formed on a P-type substrate and to be surrounded by a P-type buried layer (Buried P); and 
 forming a N-type epi layer and a N-type field implant layer sequentially on the surfaces of P-type substrate, N-type buried layer and P-type buried layer; and    doping downward a deep N + -type sinker from the surface of N-type field implant layer on the up edge of buried layer, then opening the doping windows for LPNP areas and isolation area at shielding oxide layer grown on N-type field implant layer; and    forming P − -type collector downward from the surface of epi layer and P − -type isolation area which surrounds N-type buried layer and downward extended to connect with P-type buried layer by P −  implantation and drive-in process, at this time, the deep N + -type sinker will extend downward to connect with the edge of N-type buried layer by drive-in process; and    the N-type base, which is surrounded by P − -type collector, is formed downward from the surface of epi layer by N implantation process, and    the P +  implantation into the needed area and drive-in to form P +  collector and P +  isolated area and P +  emitter downward from N-type field implant layer, while do not surpass the P − -type collector, P − -type isolated area, and N-type base respectively; and    the N + -type base area is formed on the deep N + -type sinker via N +  implantation process; and    the contact holes are formed at P +  collector area, N + -type base area, and P +  emitter area bye photolithography and etching process; and    finally forming metal electrodes of collector, base and emitter on said contact.    
   
   
       6 . The method of  claim 5 , wherein the doping windows of isolation/P − /N-type base/P +  layers defined on shielding oxide layer at the same time by a composite mask.  
   
   
       7 . The method of  claim 6 , wherein the isolation is formed by stacking P − -type doping layer and P +  doping layer.