Plasma display device and driving method thereof

Abstract

A plasma display panel. Delay circuits are added to a control terminal of a switch and a rising delay time is established to be different from a falling delay time in an address driving circuit so that voltages at adjacent address electrode may not be concurrently changed in the opposite directions. Accordingly, power consumption by the address driving circuit is minimized without a power recovery circuit.

1 . A plasma display device comprising: 
 a panel including a plurality of first electrodes in a first direction and a plurality of second electrodes in a second direction crossing the first direction; and    a plurality of selection circuits including a first selection circuit and a second selection circuit respectively including a first transistor having a first terminal coupled to a first power source for supplying an address voltage and a second terminal coupled to the second electrode, and a second transistor having a first terminal coupled to the second electrode and a second terminal coupled to a second power source for supplying a non-address voltage, the first transistor applying the address voltage to a selected second electrode, and the second transistor applying the non-address voltage to a non-selected second electrode,    wherein the time when the first transistor of the first selection circuit is turned on is different from the time when the second transistor of the second selection circuit is turned on.    
   
   
       2 . The plasma display device of  claim 1 , wherein the plasma display device further comprises a control circuit for outputting a control signal for controlling turn-on/off operations of the first and second transistors according to an input signal, and 
 a delay time until the first transistor of the first selection circuit is turned on after the input signal is applied is different from a delay time until the second transistor of the second selection circuit is turned on after the input signal is applied.    
   
   
       3 . The plasma display device of  claim 1 , wherein the control circuit comprises: 
 an inverter having an output terminal coupled to a control terminal of the second transistor; and    a first delay circuit having an input terminal for receiving the input signal, and an output terminal coupled in common to an input terminal of the inverter and a control terminal of the second transistor,    wherein a rising delay time of the first delay circuit is different from a falling delay time thereof.    
   
   
       4 . The plasma display device of  claim 3 , wherein the control circuit further comprises: 
 a second delay circuit coupled between the output terminal of the first delay circuit and the control terminal of the first transistor; and    a third delay circuit coupled between the output terminal of the inverter and the control terminal of the second transistor, and    wherein rising delay times and falling delay times of the second and third delay circuits are different.    
   
   
       5 . The plasma display device of  claim 1 , wherein a voltage at one second electrode is changed to the non-address voltage and a voltage at another second electrode then starts being changed when the voltage at one second electrode is changed from the address voltage to the non-address voltage and the voltage at another second electrode is changed from the non-address voltage to the address voltage.  
   
   
       6 . The plasma display device of  claim 1 , wherein a voltage at another second electrode is changed to the address voltage and a voltage at one second electrode then starts being changed when the voltage at one second electrode is changed from the address voltage to the non-address voltage and the voltage at another second electrode is changed from the non-address voltage to the address voltage.  
   
   
       7 . A method for driving a plasma display device including a plurality of first electrodes in a first direction and a plurality of second electrodes in a second direction crossing the first direction, wherein a rising time of a rising address pulse is different to a falling time of a falling address pulse when the rising address pulse is applied to one of second electrodes and the falling address pulse is applied to another second electrode thereof.  
   
   
       8 . The method of  claim 7 , wherein a time for the address pulse to rise after a control signal for applying the rising address pulse is different from a time for the address pulse to fall after a control signal for applying the falling address pulse.