Burst read addressing in a non-volatile memory device

Abstract

A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of rows and columns. During a read operation, a row of the memory array can be accessed and data read from a group of columns during a burst operation. The burst columns are generated using an internal counter and an externally provided start address. The memory generates the burst column addresses by modifying the least significant column address signals only. For a burst length of two, only the least significant address bit is modified. For a burst length of four, only the two least significant address bits are modified. Finally, only the three least significant address bit s are modified for a burst length of two. In one embodiment, the burst addresses rotate through the defined column group in a cyclical manner.

1 . A method for reading a non-volatile synchronous memory device having an internal counter circuit and a mode register, the method comprising: 
 generating an initial column address on column address inputs A 0 , A 1 , A 2 , A 3 , A 4 , A 5 , A 6  and A 7 , wherein A 0  is a least significant address input; 
 generating a burst read command having a burst length; and  
 the internal counter circuit counting up from the initial column address in response to the burst read command, wherein the internal counter changes a signal only on column address input A 0  if the burst length is two, the internal counter changes signals only on column address inputs A 0  and A 1  if the burst length is four, and the internal counter changes signals only on column address inputs A 0 , A 1  and A 2  if the burst length is eight, wherein when the internal counter circuit count reaches the burst length, the internal counter circuit counts from the initial column address in a cyclical manner and wherein when the internal counter circuit count reaches a maximum column address for a particular burst length, the internal counter circuit counts from 0.  
   
   
   
       2 . The method of  claim 1  and further comprising generating a read command for the mode register to read data that indicates the burst length.  
   
   
       3 . The method of  claim 1  wherein the burst length is 2 N  wherein N is a quantity of least significant address signals.  
   
   
       4 . The method of  claim 1  wherein the burst length determines a quantity of memory columns that are selected in the memory device.  
   
   
       5 . The method of  claim 1  wherein the burst length is written into the mode register.  
   
   
       6 . The method of  claim 1  wherein the mode register is comprised of both a non-volatile memory and a volatile memory.  
   
   
       7 . A method for reading a non-volatile synchronous memory device having an internal counter circuit that generates column addresses and a mode register containing a burst length, the method comprising: 
 generating an initial column address on column address inputs A 0 , A 1 , A 2 , A 3 , A 4 , A 5 , A 6 , and A 7 , wherein A 0  is a least significant address input; and 
 generating a command to cause the internal counter circuit to generate additional column addresses starting at the initial column address, wherein the internal counter changes only on column input A 0  if the burst length is two, the internal counter changes only on column address inputs A 0  and A 1  if the burst length is four, and the internal counter changes only on column address inputs A 0 , A 1  and A 2  if the burst length is eight wherein when the internal counter circuit count reaches the burst length, counting from the initial column address in a cyclical manner and wherein the additional column addresses are generated in accordance with an order of column address accesses provided as, where the column address access number indicates a binary state of the column address inputs:  
                                     Initial             Column     Burst   Address   Order of column                           Length   A2   A1   A0   address accesses           2           0   0-1                 1   1-0     4       0   0   0-1-2-3             0   1   1-0-3-2             1   0   2-3-0-1             1   1   3-2-1-0     8   0   0   0   0-1-2-3-4-5-6-7         0   0   1   1-0-3-2-5-4-7-6         0   1   0   2-3-0-1-6-7-4-5         0   1   1   3-2-1-0-7-6-5-4         1   0   0   4-5-6-7-0-1-2-3         1   0   1   5-4-7-6-1-0-3-2         1   1   0   6-7-4-5-2-3-0-1         1   1   1   7-6-5-4-3-2-1-0                                                      
   
   
   
       8 . The method of  claim 7  wherein the internal counter circuit is part of command execution logic.  
   
   
       9 . The method of  claim 7  wherein the non-volatile synchronous memory device is a flash memory device.  
   
   
       10 . The method of  claim 9  wherein the flash memory device is compatible with an SDRAM.  
   
   
       11 . A method for reading a synchronous flash memory device having an internal counter circuit, the method comprising: 
 generating an initial column address on column address inputs A 0 , A 1 , A 2 , A 3 , A 4 , A 5 , A 6  and A 7 , wherein A 0  is a least significant address input; and 
 generating a burst read command, including a burst length, to cause the internal counter circuit to count up from the initial column address, wherein the internal counter changes only on column address input A 0  if the burst length is two, the internal counter changes only on column address inputs A 0  and A 1  if the burst length is four, and the internal counter changes only on column address inputs A 0 , A 1  and A 2  if the burst length is eight and wherein when the internal counter circuit count reaches the burst length, returning to count from the initial column address in a non-linear manner.  
   
   
   
       12 . The method of  claim 11  wherein the flash memory device further comprises a register.  
   
   
       13 . The method of  claim 12  and further including writing the burst read command to the register.  
   
   
       14 . The method of  claim 13  and further including receiving an indication from the flash memory device of whether the device is protected.  
   
   
       15 . A method for reading a synchronous flash memory device having an internal counter circuit and a command register and a mode register, the method comprising: 
 loading the command register;    receiving an active command and a row address;    determining if the flash memory device is protected;    if the flash memory device is not protected, generating an initial column address on column address inputs A 0 , A 1 , A 2 , A 3 , A 4 , A 5 , A 6  and A 7 , wherein A 0  is a least significant address input; and 
 writing a burst read command to the flash memory device, the burst read command including a burst length and the initial column address, to cause the internal counter circuit to count up from the initial column address, wherein the internal counter changes only on column address input A 0  if the burst length is two, the internal counter changes only on column address inputs A 0  and A 1  if the burst length is four, and the internal counter changes only on column address inputs A 0 , A 1  and A 2  if the burst length is eight and wherein when the internal counter circuit count reaches the burst length, returning to count from the initial column address in a in a cyclical manner.  
   
   
   
       16 . The method of  claim 15  and further including the flash memory device storing the burst length and the initial column address in the mode register.  
   
   
       17 . The method of  claim 15  wherein the mode register comprises a non-volatile portion and a volatile portion.  
   
   
       18 . The method of  claim 17  and further including automatically loading data from the non-volatile portion to the volatile portion when the flash memory device is powered up.  
   
   
       19 . The method of  claim 15  wherein the flash memory device further includes a status register.  
   
   
       20 . The method of  claim 19  and further including monitoring the status register to determine if errors are detected.