Short channel insulated-gate static induction transistor and method of manufacturing the same

Abstract

The ultra high-speed vertical short channel insulated-gate static induction transistor with uniform operating characteristic which has the drain layer 3 consisting of an epitaxial single crystal layer on the main surface 2 of substrate 1 , the channel layer 4 with thickness 1000 Å or less on the drain layer, the source layer 5 consisting of an epitaxial single crystal layer on the channel layer 4 , and the insulated-gates 6 and 7 on the sidewalls of the drain, the channel, and the source layers. Since the thickness of 1000 Å or less is accurately controlled using the molecular layer epitaxial method and the channel layer 4 is grown up, the X-ray photolithography is not needed. Since the gate oxide film is formed by low temperature CVD using active oxygen, impurity re-distribution does not occur.

1 - 3 . (canceled)  
   
   
       4 . A planar type short channel insulated-gate static induction transistor comprising: 
 a channel layer of channel length 1000 Å or less;    a source layer;    and a drain layer,    wherein said channel layer, said source layer and said drain layer being arranged in parallel with a main surface of a substrate,    and an insulated-gate in which width is as same as that of said channel length being provided right on said channel layer.    
   
   
       5 . A planar type short channel insulated-gate static induction transistor as set forth in  claim 4 , characterized in that said substrate being Si single crystal, said main surface being a (100) or its equivalent plane, said channel layer being p type Si single crystal layer, said source layer and said drain layer being an n type Si single crystal layer, and said insulated-gate consisting of the SiO 2  and the polysilicon.  
   
   
       6 . A planar type short channel insulated-gate static induction transistor as set forth in  claim 4 , characterized in that said substrate being Si single crystal, said main surface being a (100) or its equivalent plane, said channel layer being an n type Si single crystal layer, said source layer and said drain layer being a p type Si single crystal layer, and said insulated-gate consisting of the SiO 2  and the polysilicon.  
   
   
       7 . A method of manufacturing a vertical type short channel insulated-gate static induction transistor, comprising the steps of: 
 growing a drain layer epitaxially on a main surface of a semiconductor substrate with a specific plane direction;    growing a channel layer by controlling epitaxial growth of every mono molecular layer on said drain layer; 
 depositing a passivation film on said source layer;  
   making openings in said passivation film and forming a U-shaped groove perpendicular to said main surface to the depth to said semiconductor substrate; 
 depositing a gate oxide film on said U-shaped groove;  
   depositing a gate electrode layer on said gate oxide film, and an insulated-gate consisting of said gate oxide film and said gate electrode being formed by leaving said gate oxide film layer and said gate electrode layer on a sidewall of said U-shaped groove.    
   
   
       8 . A method as set forth in  claim 7 , characterized in that said process to grow said channel layer by controlling epitaxial growth of every mono molecular layer are comprising the steps of exposing said semiconductor substrate surface set in a vacuum vessel to a compound gas of a semiconductor element for a certain time and evacuating a certain time, and then exposing said semiconductor substrate surface to a compound gas of a dopant element for a certain time and evacuating a certain time.  
   
   
       9 . A method as set forth in  claim 7 , characterized in that said process to form said U-shaped groove is an anisotropic plasma etching with a high etching speed in the direction perpendicular to said main surface.  
   
   
       10 . A method as set forth in  claim 7 , characterized in that said process to deposit said gate oxide film is a low temperature CVD process in which a compound gas of a semiconductor element and an active oxygen gas react on a surface of said semiconductor substrate.  
   
   
       11 . A method as set forth in  claim 7 , characterized in that said process to deposit said gate electrode layer is a low temperature CVD to deposit polycrystalline semiconductor by decomposing the compound gas of a semiconductor element on a surface of said semiconductor substrate, wherein said gate electrode layer is deposited also on a sidewall of said U-shaped groove.  
   
   
       12 . A method as set forth in  claim 7 , characterized in that said process to leave said gate oxide film layer and gate electrode layer on the sidewall of U-shaped groove is an anisotropic plasma etching with a high etching speed in the direction perpendicular to said main surface, wherein said gate oxide film layer and gate electrode layer is left on the sidewall of U-shaped groove by the etching of making use a difference of the thickness of said gate electrode layer.  
   
   
       13 . A method as set forth in any one of claims  8 ,  10 , or  11 , characterized in that said compound gas of a semiconductor element is Si 2 H 6  (disilane).  
   
   
       14 . A method as set forth in  claim 8 , characterized in that said compound gas of a dopant element is PH 3  (phosphine) in case of an type dopant, and B 2 H 6  (diborane) in case of a p type dopant.  
   
   
       15 . A method of manufacturing a planar type short channel insulated-gate static induction transistor, comprising the steps of: 
 growing a drain layer epitaxially on a main surface of a semiconductor substrate with a specific plane direction;    depositing a passivation film on said drain layer;    making openings in said passivation film and forming a U-shaped groove perpendicular to said main surface to the depth to said semiconductor substrate;    growing a channel layer and a source layer on said U-shaped groove by controlling epitaxial growth of every mono molecular layer;    depositing a gate oxide film on said channel layer and said source layer;    depositing a gate electrode layer on said gate oxide film, 
 and an insulated-gate consisting of said gate oxide film and said gate electrode being formed by leaving said gate oxide film layer and said gate electrode layer on a sidewall of said U-shaped groove.  
   
   
   
       16 . A method as set forth in  claim 15 , characterized in that said process to form said U-shaped groove is an anisotropic plasma etching with a high etching speed in the direction perpendicular to said main surface.  
   
   
       17 . A method as set forth in  claim 15 , characterized in that said process to grow said channel layer and said drain layer by growing a channel layer and a source layer on said U-shaped groove by controlling epitaxial growth of every mono molecular layer comprises the steps of exposing said semiconductor substrate surface set in a vacuum vessel to a compound gas of a semiconductor element for a certain time and evacuating a certain time, and then exposing said semiconductor substrate surface to a compound gas of a dopant element for a certain time and evacuating a certain time.  
   
   
       18 . A method as set forth in  claim 15 , characterized in that said process to deposit said gate oxide film is a low temperature CVD in which a compound gas of a semiconductor element and an active oxygen gas react on a surface of said semiconductor substrate so as to grow said gate oxide film.  
   
   
       19 . A method as set forth in  claim 15 , characterized in that said process to deposit said gate electrode layer is a low temperature CVD to deposit polycrystalline semiconductor by decomposing the compound gas of a semiconductor element on a surface of said semiconductor substrate, wherein said gate electrode layer is deposited also on a sidewall of said U-shaped groove.  
   
   
       20 . A method as set forth in  claim 15 , characterized in that said process to leave said gate oxide film layer and gate electrode layer on said sidewall of U-shaped groove is an anisotropic plasma etching with a high etching speed in the direction perpendicular to said main surface, wherein said gate oxide film layer and gate electrode layer is left on said sidewall of U-shaped groove by the etching of making use a difference of the thickness of said gate electrode layer.  
   
   
       21 . A method as set forth in  claim 15 , characterized in that said semiconductor substrate with a specific oriented plane is a Si (100) substrate or its equivalent plane substrate.  
   
   
       22 . A method as set forth in any one of claims  17 ,  18  or  19 , characterized in that said compound gas of a semiconductor element is Si 2 H 6  (disilane).  
   
   
       23 . A method according to  claim 17 , characterized in that said compound gas of a dopant element is PH 3  (phosphine) in case of a n type dopant, and B 2 H 6  (diborane) in case of a p type dopant.