Low power dynamic logic gate with full voltage swing operation

Abstract

Dynamic low-power logic using recycled energy is disclosed. Logic circuits have a discharge path, a precharge path and a control circuit. The precharge path is a PMOS transistor coupled between the clock line and the output node of the circuit and configured to charge the output node to the loic high voltage of the clock line during a precharge phase. During an evaluation phase, the discharge path computes the desired logic function at the output node. A control circuit is connected between the output node and the clock line and to the gate of the precharge path transistor. The control circuit provides the proper gate drive, regardless of the voltage on the output node or the inputs to the discharge path, to guarantee that the precharge transistor fully charges the output node to the logic high voltage of the clock line, which provides recycled energy for operating the circuit.

1 . A logic circuit comprising: 
 a discharge path connected between a first node and a second node, the discharge path being operative using energy flowing from the second node to the first node to evaluate a logic function of at least one input during an evaluation phase;    a precharge path connected between the first node and the second node and being conductive during a precharge phase so as to transfer energy from the first node to the second node; and    a control circuit having an output connected to the precharge path, the control circuit being operative to establish and maintain the conductivity of the precharge path during the precharge phase independent of the states of the at least one input and the output node.    
   
   
       2 . A logic circuit as recited in  claim 1 , wherein the evaluation phase occurs when a signal on the first node is at a first voltage and the precharge phase occurs when the signal on the first node is at a second voltage.  
   
   
       3 . A logic circuit as recited in  claim 2 , wherein the first voltage is a logic low and the second voltage is a logic high.  
   
   
       4 . A logic circuit as recited in  claim 1 , wherein a signal applied to the first node determines a time for the evaluation phase and a time for the precharge phase.  
   
   
       5 . A logic circuit as recited in  claim 1 , 
 wherein a signal applied to the first node is a periodic signal whose period includes a first phase and a second phase; and    wherein the first phase is the evaluation phase and the second phase is the precharge phase.    
   
   
       6 . A logic circuit as recited in  claim 1 , wherein the first node is connected to an energy storage circuit that captures any energy flowing from the second node to the first node during the evaluation phase and provides any energy that is transferred from the second node to the first node during the precharge phase.  
   
   
       7 . A logic circuit as recited in  claim 6 , 
 wherein the energy storage circuit is a resonant circuit; and    wherein the resonant circuit oscillates with a period that defines the precharge phase and the discharge phase.    
   
   
       8 . A logic circuit as recited in  claim 7 , wherein the resonant circuit period is synchronous to a reference clock period.  
   
   
       9 . A logic circuit as recited in  claim 1 , 
 wherein the precharge path is a PMOS transistor, said transistor having a gate, source and drain, and a channel defined between the source and drain, the channel of the PMOS transistor being connected between the first and second nodes and made conductive during the precharge phase; and    wherein the control circuit includes a pair of complementary diode-connected transistors, each said transistor having a source, drain and channel defined therebetween, the sources of said transistors being connected to the second node and the drains being connected to the gate of the PMOS transistor of the precharge path.    
   
   
       10 . A logic circuit as recited in  claim 1 , 
 wherein the logic function is an AND function of two inputs; and    wherein the discharge path includes a pair of NMOS transistors, each said transistor having a gate, source, and drain, and a channel between the source and drain, the channels of the NMOS transistors being connected in series, and the series connected channels being connected between the first and second nodes, each gate of said pair of transistors being connected to one of the two inputs, and    wherein said discharge path is operative to transfer energy from the second node to the first node when the both inputs are at a logic high during the evaluation phase.    
   
   
       11 . A logic circuit as recited in  claim 1 , 
 wherein the logic function is an OR function of two inputs; and    wherein the discharge path includes a pair of NMOS transistors, each said transistor having a gate, source, and drain, and a channel between the source and drain, the channels of the NMOS transistors being connected in parallel, and the parallel-connected channels being connected between the first and second nodes, each gate of said pair of transistors being connected to one of the two inputs, and    wherein said discharge path is operative to transfer energy from the second node to the first node when either of the two inputs is at a logic high during the evaluation phase.    
   
   
       12 . A method of evaluating a logic function, comprising: 
 providing a conductive path between a first node and a second node during a precharge phase to transfer energy between the first and second node, the first node being connected to energy storage circuitry that provides any energy to be transferred, the conductive path being established and maintained by a control circuit during the precharge phase; and    evaluating a logic function of at least one input during an evaluation phase during which energy may flow between the second node and the first node, any said energy flowing being captured by the energy storage circuitry.    
   
   
       13 . A method of evaluating a logic function, as recited in  claim 12 , wherein the energy storage circuitry is a resonant circuit.  
   
   
       14 . A method of evaluating a logic function, as recited in  claim 12 , wherein the first node oscillates with a period that defines the precharge phase and the discharge phase.  
   
   
       15 . A method of evaluating a logic function, as recited in  claim 12 , wherein the first node oscillates with a period that defines the precharge phase and the discharge phase and the period is synchronous to a reference clock.