Low power clocking systems and methods

Abstract

A low power a reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.

1 - 20 . (canceled)  
     
     
         21 . An integrated circuit comprising: 
 a reconfigurable processor core including a plurality of processor units having clock inputs to receive a clock frequency to clock operation of the respective unit; and    a controller having a plurality of clock outputs coupled to respective clock inputs of at least some of the plurality of processor units, wherein the controller is capable of independently controlling the clock frequency for the at least some of the plurality of processor units.    
     
     
         22 . The integrated circuit of  claim 21 , wherein at least one of the plurality of processor units comprises a digital signal processor (DSP).  
     
     
         23 . The integrated circuit of  claim 22 , wherein at least another one of the plurality of processor units comprises a reduced instruction set computer (RISC) processor.  
     
     
         24 . The integrated circuit of  claim 21 , wherein at least one of the plurality of processor units is to be dynamically manageable on a per-task basis.  
     
     
         25 . The integrated circuit of  claim 21 , wherein the controller is capable of independently controlling the clock frequency for at least some of the plurality of processor units on a pre-assigned basis.  
     
     
         26 . The integrated circuit of  claim 21 , further comprising a buffer coupled between an output of a first one of the plurality of processor units and an input to a second one of the plurality of processor units.  
     
     
         27 . The integrated circuit of  claim 21 , wherein the integrated circuit further comprises: 
 a first radio frequency wireless transceiver coupled to the plurality of processor units; and    a second radio frequency wireless transceiver coupled to the plurality of processor units.    
     
     
         28 . The integrated circuit of  claim 27 , wherein the plurality of processor units, the first radio frequency wireless transceiver, and the second radio frequency wireless transceiver are integrated on a single substrate.  
     
     
         29 . The integrated circuit of  claim 21 , wherein the controller is capable of independently controlling the clock frequency for at least some of the plurality of processor units based upon a system stimulus.  
     
     
         30 . The integrated circuit of  claim 21 , wherein the controller is capable of pre-assigning a clock frequency to at least one of the plurality of processor units based upon a task to be performed by the at least one processor unit.  
     
     
         31 . The integrated circuit of  claim 21 , wherein the plurality of processor units comprises at least two processor units capable of operating in parallel and at least two serial processor units coupled such that an output of the first serial processor unit is coupled to an input of the second serial processor unit.  
     
     
         32 . The integrated circuit of  claim 31 , wherein each of the plurality of processor units is coupled to receive an independently controllable supply voltage.  
     
     
         33 . A system comprising: 
 a display; and    an integrated circuit on a single substrate coupled to the display, the integrated circuit including: 
 a plurality of processor units including a first processor unit having a first clock input to receive a first clock signal to clock operation of the first processor unit, a second processor unit having a second clock input to receive a second clock signal to clock operation of the second processor unit, and a third processor unit having a third clock input to receive a third clock signal to clock operation of the third processor unit; and  
 a controller to generate and independently rate control the first clock signal, the second clock signal and the third clock signal, wherein the controller is capable of varying the first clock signal, the second clock signal and the third clock signal; and  
 a first radio frequency wireless transceiver coupled to the plurality of processor units.  
   
     
     
         34 . The system of  claim 33 , wherein the integrated circuit further comprises a second radio frequency wireless transceiver coupled to the plurality of processor units.  
     
     
         35 . The system of  claim 33 , further comprising a buffer coupled between an output of the third processor unit and an input to a fourth processor unit, the fourth processor unit on the single substrate.  
     
     
         36 . The system of  claim 35 , wherein the first processor unit and the second processor unit comprise parallel processors and the third processor unit and the fourth processor unit comprise serial processors.  
     
     
         37 . A method comprising: 
 generating at least a first clock signal, a second clock signal and a third clock signal via a controller on an integrated circuit; and    providing the first clock signal to a first processor unit and a second processor unit of the integrated circuit; and    providing the second clock signal and the third clock signal to a third processor unit and a fourth processor unit on the integrated circuit, respectively.    
     
     
         38 . The method of  claim 37 , further comprising varying at least one of the first, second, and third clock signals using the controller.  
     
     
         39 . The method of  claim 37 , further comprising independently rate controlling each of the first clock signal, the second clock signal and the third clock signal.  
     
     
         40 . The method of  claim 37 , further comprising providing a clock signal controlled by the controller to a radio frequency wireless transceiver on the integrated circuit.