Oscillator

Abstract

An oscillator, generating multiple phases of clock signals having a uniform phase difference with a high precision by a simple configuration, includes a plurality of NAND circuits ND 1 to ND 8 having the same number of input terminals connected in a ring. Eight NAND circuits are connected, and an output node of each NAND circuit is connected to an input node of each NAND circuit up to the NAND circuit connected exactly two places, that is, the number of input terminals' worth of places, ahead.

1 - 4 . (canceled)  
   
   
       5 . An oscillator formed by connecting a plurality of M logical circuits in a ring formation outputting M clock signals to outside the present oscillator, the M logic circuits being a same type with a plurality of K input terminals, each of the M logic circuits generating one of the M clock signals, wherein: 
 an output value pattern of 2M bits is matched with a part of a logic pattern;    the output value pattern of 2M bits being formed by combining an output value pattern of M bits of the clock signals at a first timing and an output value pattern of M bits at a second timing which is a certain time period after the first timing;    the logic pattern being formed by repeating a pattern of L bits;    the L bit pattern including K bits of either logic value 0 or logic value 1 and one bit of the other; and    the M and the L being not integer multiples of each other; wherein L is equal to K+1.    
   
   
       6 . The oscillator as set forth in  claim 5 , wherein: 
 the K input terminals of each logical circuit are respectively connected to K outputs of K logical circuits, the K logical circuits being sequentially disposed at an upper stream side starting from and immediately before the present logical circuit.    
   
   
       7 . The oscillator as set forth in claim  1 , wherein said M is an even number.  
   
   
       8 . The oscillator as set forth in claim  1 , wherein all of said logical circuits are configured with a NAND circuit or NOR circuit.