US2006067592A1PendingUtilityA1

Configurable image processor

42
Individually held — no corporate assignee on recordPriority: May 27, 2004Filed: Sep 7, 2004Published: Mar 30, 2006
Est. expiryMay 27, 2024(expired)· nominal 20-yr term from priority
Inventors:Simon Robert WalmsleyMichael John WebbBruce Mervyn Horsburgh
G06K 15/1857G06K 15/102B41J 2/2139G06K 2215/0085
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Claims

Abstract

An image processor, including: memory; a plurality of processing modules; and a general purpose processor; the image processor being configurable into: a first mode, in which at least some of the modules form a processing pipeline for processing image data; a second mode, in which the general purpose processor processes data output by, or supplies processed data to, at least one of the processing modules in the pipeline.

Claims

exact text as granted — not AI-modified
1 . An image processor, including: 
 memory;    a plurality of processing modules; and    a general purpose processor;    the image processor being configurable into:    a first mode, in which at least some of the modules form a processing pipeline for processing image data;    a second mode, in which the general purpose processor processes data output by, or supplies processed data to, at least one of the processing modules in the pipeline.    
   
   
       2 . An image processor according to  claim 1 , wherein, in the second mode, the processor positionally replaces at least one of the processing modules in the processing pipeline.  
   
   
       3 . An image processor according to  claim 2 , wherein, in the second mode, the processor is configured to: 
 receive first data processed by one of the processing modules;    process the first data in accordance with programming instructions, thereby generating second data;    outputt the second data for processing by another of the processing modules.    
   
   
       4 . An image processor according to  claim 1 , wherein at least one of the processing modules is operable such that: 
 in the first mode, the at least one processing module receives data from a preceding processing module in the pipeline; and    in the second mode, the at least one processing module receives data from the processor.    
   
   
       5 . An image processor according to  claim 4 , wherein the data received by the at least one processing module is retrieved from the memory.  
   
   
       6 . An image processor according to  claim 1 , wherein at least one of the processing modules is operable such that: 
 in the first mode, the at least one processing module outputs data for use by a subsequent processing module in the pipeline; and    in the second mode, the at least one processing module outputs data for use by the processor.    
   
   
       7 . An image processor according to  claim 6 , wherein the data output by the at least one processing module is stored in the memory for access by the subsequent processing module or the general purpose processor.  
   
   
       8 . An image processor according to  claim 1 , wherein each of at least some of the processing modules is configured to receive data from a corresponding receive block, wherein: 
 in the first mode, the receive block is configured to: coordinate with a processing module upstream in the pipeline to determine when the upstream processing module has made available data in the memory;    and read the data from the memory when it is available; and    in the second mode, the receive block is configured to: receive information from the general purpose processor indicative of data being made available in the memory; and read the available data from the memory when it is available.    
   
   
       9 . An image processor according to  claim 8 , configurable into a third mode, in which the receive block receives data directly from an upstream module.  
   
   
       10 . An image processor according to  claim 9 , wherein the receive block includes a buffer for receiving the data directly from the upstream module.  
   
   
       11 . An image processor according to  claim 9 , configurable into a fourth mode, in which the receive block receives data directly from the processor.  
   
   
       12 . An image processor according to  claim 11 , wherein the receive block includes a buffer for receiving the data directly from the processor.  
   
   
       13 . An image processor according to  claim 8 , configurable into a third mode, in which the receive block receives data directly from the processor.  
   
   
       14 . An image processor according to  claim 1 , including at least one communications block configured to receive processed data from the processor or one or more of the processing modules and to output the processed data from the image processor.  
   
   
       15 . An image processor according to  claim 14 , wherein the communications block receives from the memory the data to be output.  
   
   
       16 . An image processor according to  claim 14 , wherein the image processor takes the form of a monolithic integrated circuit, and the at least one communications block is configured to output the processed data from the integrated circuit.  
   
   
       17 . An image processor according to  claim 1 , including at least one communications block configured to receive processed data from outside the image processor and supply it to the processor and/or one or more of the processing modules.  
   
   
       18 . An image processor according to  claim 17 , wherein the communications block writes to the memory the data to be supplied to the processor and/or the one or more of the processing modules.  
   
   
       19 . An image processor according to  claim 14 , wherein the image processor takes the form of a monolithic integrated circuit, and the at least one communications block is configured to output the processed data from the integrated circuit.  
   
   
       20 . An image processor having a general purpose processor and a plurality of operative modules, the image processor being configurable to form an image processing pipeline such that at least one first operative module selectively receives data from either another of the operative modules or the general purpose processor.  
   
   
       21 . An image processor according to  claim 20 , further including a memory, wherein the at least one first operative module receives the data from the memory.  
   
   
       22 . An image processor according to  claim 21 , wherein each of the at least one of the first modules is configured to retrieve the data from respective addresses or ranges of addresses in the memory, the respective addresses or ranges of addresses being configurable for each of the at least one first module.  
   
   
       23 . An image processor according to  claim 22 , wherein each of the at least one first modules includes a receive module and a processing module, the receive module being configured to receive the data from the memory and the processing module being configured to receive the data from the receive module.  
   
   
       24 . An image processor according to  claim 20 , wherein each of the at least one first modules includes a buffer, the buffer being configured to receive the data from the upstream operative module or processor.  
   
   
       25 . An image processor according to  claim 20 , the image processor taking the form of a print engine controller.

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