Photogate stack with nitride insulating cap over conductive layer

Abstract

A photogate structure having increased quantum efficiency, especially for low wavelength light such as blue light. The photogate is formed of a thin conductive layer, such as a layer of doped polysilicon. A nitride insulating cap is formed over the conductive layer. The nitride layer reduces the reflections at the conductor/insulator interface. A pixel cell incorporating the photogate structure also has a buried accumulation region beneath the photogate. A method of fabricating the photogate structure is also disclosed.

1 . A photosensor for use in an imaging device, said photosensor comprising: 
 a doped region formed in a substrate for accumulating photo-charges;    a doped polysilicon layer provided over said doped region; and    a nitride layer provided over said doped polysilicon layer.    
   
   
       2 . The photosensor of  claim 1 , wherein said doped polysilicon layer has a thickness of about 100 Angstroms to about 1500 Angstroms.  
   
   
       3 . The photosensor of  claim 2 , wherein said doped polysilicon layer has a thickness of about 600 Angstroms.  
   
   
       4 . The photosensor of  claim 1 , wherein the nitride layer comprises a nitride/oxide sandwich structure.  
   
   
       5 . The photosensor of  claim 4 , wherein the nitride layer comprises a nitride layer having a thickness of about 1000 Angstroms and an oxide layer having a thickness of about 1000 Angstroms.  
   
   
       6 . The photosensor of  claim 1 , further comprising a transparent conductive layer formed over the doped polysilicon layer.  
   
   
       7 . The photosensor of  claim 6 , wherein the transparent conductive layer is comprised of one of indium tin oxide, indium oxide, and tin oxide.  
   
   
       8 . A photogate comprising: 
 an accumulation region formed in a substrate, said region for accumulating region for accumulating charges formed in response to applied light;    a gate oxide layer formed over said accumulation region;    a transparent gate formed over said gate oxide layer, wherein the transparent gate comprises a layer of polysilicon having a thickness of about 100 Angstroms to about 1500 Angstroms; and    a nitride cap formed over said transparent gate.    
   
   
       9 . The photogate of  claim 8 , wherein the transparent gate further comprises a transparent conductive layer over the polysilicon layer.  
   
   
       10 . The photogate of  claim 8 , wherein the nitride cap comprises an NO layer formed over said transparent gate.  
   
   
       11 . The photogate of  claim 8 , further comprising insulating sidewalls formed on at least one side of said transparent gate and said nitride cap.  
   
   
       12 . A pixel sensor cell comprising: 
 a doped region formed in a substrate; and    a stacked photogate provided over said first doped region, said stacked photogate comprising a nitride insulating layer over a doped polysilicon layer.    
   
   
       13 . The pixel sensor cell of  claim 12 , wherein the nitride insulating layer comprises an NO layer.  
   
   
       14 . The pixel sensor cell of  claim 12 , wherein the nitride insulating layer has a thickness within the range of about 500 Angstroms to about 3000 Angstroms.  
   
   
       15 . The pixel sensor cell of  claim 14 , wherein the nitride insulating layer comprises a nitride layer having a thickness of about 1000 Angstroms and an oxide layer having a thickness of about 1000 Angstroms.  
   
   
       16 . The pixel sensor cell of  claim 12 , wherein said stacked photogate further comprises a transparent conductive layer over the doped polysilicon layer.  
   
   
       17 . The pixel sensor cell of  claim 16 , wherein the transparent conductive layer comprises any one of indium oxide, tin oxide, or indium tin oxide.  
   
   
       18 . The pixel sensor cell of  claim 17 , wherein said transparent conductive layer comprises indium tin oxide.  
   
   
       19 . A pixel sensor cell comprising: 
 a first doped region formed in a substrate, said first doped region for accumulating photo-charges;    a thin layer of doped polysilicon formed over said first doped region;    an insulating cap formed over said doped polysilicon layer, said insulating cap comprising nitride; and    a transistor adjacent one side of said first doped region, said transistor for transferring the accumulated photo-charges from said first doped region to a storage region.    
   
   
       20 . The pixel sensor cell of  claim 19 , wherein said thin layer of polysilicon is located at least partially over said transistor.  
   
   
       21 . The pixel sensor cell of  claim 20 , wherein said insulating cap comprises NO.  
   
   
       22 . The pixel sensor cell of  claim 19 , wherein said transistor comprises a gatestack having an insulating layer comprising nitride over a thin layer of polysilicon.  
   
   
       23 . The pixel sensor cell of  claim 19 , further comprising a second doped region in said substrate, said second doped region located between said first doped region and said transfer transistor.  
   
   
       24 . An array of pixel sensor cells comprising: 
 a plurality of pixel cells formed in a substrate, each cell comprising: 
 a photogate for generating and accumulating photo-charges, said photogate comprising: 
 a doped polysilicon layer provided over a first doped region in the substrate, and  
 a nitride layer provided over said doped polysilicon layer; and  
 
 a transistor for transferring the accumulated photo-charges to a second doped region in the substrate.  
   
   
   
       25 . The array of pixel cells of  claim 24 , wherein said polysilicon layer has a thickness of about 100 Angstroms to about 1500 Angstroms.  
   
   
       26 . The array of pixel cells of  claim 25 , wherein said polysilicon layer has a thickness of about 600 Angstroms.  
   
   
       27 . The array of pixel cells of  claim 24 , wherein the nitride layer comprises an NO layer.  
   
   
       28 . The array of pixel cells of  claim 24 , wherein the doped polysilicon layer is located at least partially over a gatestack of said transistor.  
   
   
       29 . The array of pixel cells of  claim 28 , wherein the nitride layer is located at least partially over a gatestack of said transistor.  
   
   
       30 . The array of pixel cells of  claim 24 , wherein said transistor has a gatestack that comprises a nitride insulating cap over a layer of polysilicon.  
   
   
       31 . The array of pixel cells of  claim 24 , wherein said transistor is electrically connected to said photogate through a third doped region in the substrate.  
   
   
       32 . The array of pixel cells of  claim 24 , wherein said photogate further comprises a transparent conductive layer.  
   
   
       33 . The array of pixel cells of  claim 32 , wherein said transparent conductive layer is formed over said polysilicon layer.  
   
   
       34 . The array of pixel cells of  claim 33 , wherein said transparent conductive layer is formed beneath said nitride layer.  
   
   
       35 . The array of pixel cells of  claim 33 , wherein said transparent conductive layer comprises at least one of indium tin oxide, indium oxide, and tin oxide.  
   
   
       36 . An imaging system comprising: 
 a plurality of pixel cells arranged into an array of rows and columns, each pixel cell comprising a photogate, said photogate comprising: a dielectric layer; a transparent conductive layer over the dielectric layer; and a nitride cap over the transparent conductive layer; and    a plurality of output circuits, each output circuit being connected to a respective cell of said array.    
   
   
       37 . The imaging system of  claim 36 , wherein the transparent conductive layer is a layer of doped polysilicon.  
   
   
       38 . The imaging system of  claim 37 , wherein the layer of doped polysilicon has a thickness in the range of 100 Angstroms to about 1500 Angstroms.  
   
   
       39 . The imaging system of  claim 36 , wherein the transparent conductive layer is a layer of indium tin oxide over a layer of doped polysilicon.  
   
   
       40 . The imaging system of  claim 36 , wherein the nitride cap comprises a layer of NO located over the transparent conductive layer.  
   
   
       41 . The imaging system of  claim 36 , each pixel cell further comprising a transistor having a gatestack adjacent said photogate, wherein said transparent conductive layer is located at least partially over the gatestack.  
   
   
       42 . The imaging system of  claim 41 , wherein said nitride cap is located at least partially over the gatestack.  
   
   
       43 . A CMOS imager comprising: 
 an array of CMOS pixel sensor cells formed in a substrate, wherein at least one pixel sensor cell comprises: 
 a photogate for generating photo-charges, said photogate comprising: a thin layer of polysilicon located at least partially over a doped region in the substrate and a nitride layer located over said polysilicon layer; and  
 at least one transistor for reading out from the pixel cell a signal representing the amount of charge generated by said photogate; and  
   signal processing circuitry for processing signals received from said pixels sensor cells of said array.    
   
   
       44 . The CMOS imager of  claim 43 , wherein said photogate further comprises a transparent conductive layer.  
   
   
       45 . The CMOS imager of  claim 44 , wherein said transparent conductive layer is a layer of indium tin oxide and is located between said polysilicon layer and said nitride layer.  
   
   
       46 . The CMOS imager of  claim 43 , wherein said nitride layer is an NO layer.  
   
   
       47 . The CMOS imager of  claim 43 , wherein said at least one transistor has a gatestack that comprises a layer of nitride located over a layer of polysilicon.  
   
   
       48 . The CMOS imager of  claim 43 , wherein said at least one transistor comprises a transfer transistor having a gatestack being located at least partially under said thin layer of polysilicon.  
   
   
       49 . A method of forming a photogate, said method comprising the steps of: 
 forming a thin layer of doped polysilicon at a top surface of a substrate;    forming a material layer comprising nitride over the doped polysilicon layer; and    forming a doped region for accumulating photo-charges in the substrate and at least partially under the doped polysilicon layer.    
   
   
       50 . The method of  claim 49 , further comprising the step of forming a transparent conductive layer over the layer of doped polysilicon.  
   
   
       51 . The method of  claim 49 , wherein said step of forming a thin layer of doped polysilicon comprises: 
 depositing a layer of polysilicon; and    thinning the polysilicon layer to a thickness of about 100 Angstroms to about 1500 Angstroms.    
   
   
       52 . The method of  claim 51 , wherein the thickness is about  600  Angstroms.  
   
   
       53 . The method of  claim 49 , further comprising the step of forming an isolation region in the substrate, wherein the thin layer of doped polysilicon is formed at least partially over the isolation region.  
   
   
       54 . The method of  claim 49 , wherein said step of forming a material layer comprising nitride comprises: 
 depositing a layer of nitride; and    depositing a layer comprising an oxide over the layer of nitride.    
   
   
       55 . The method of  claim 49 , wherein said step of forming a material layer comprises: 
 depositing a layer of nitride; and    oxidizing the nitride layer.    
   
   
       56 . A method of forming a pixel sensor cell, said method comprising the steps of: 
 forming a photogate, wherein the photogate comprises a thin conductive layer formed over a top surface of a substrate and an insulative cap formed over the conductive layer and comprising nitride; and    forming at least one transistor electrically connected to the photogate.    
   
   
       57 . The method of  claim 56 , wherein the conductive layer comprises a layer of doped polysilicon.  
   
   
       58 . The method of  claim 57 , wherein the conductive layer further comprises a layer comprising indium-tin-oxide.  
   
   
       59 . The method of  claim 56 , wherein the step of forming a photogate comprises forming a conductive layer at least partially over the at least one transistor.  
   
   
       60 . The method of  claim 56 , wherein said step of forming a photogate comprises: 
 depositing a layer of polysilicon using CVD; and    doping the polysilicon layer.    
   
   
       61 . A method of forming a pixel sensor cell, the method comprising: 
 forming at least one isolation region in a doped substrate, the substrate being doped to a first conductivity type;    forming a dielectric layer at a surface of the substrate;    forming a thin transparent conductive layer over the dielectric layer;    forming an insulating layer comprising nitride over the transparent conductive layer;    selectively etching said transparent conductive and insulating layers to form a photogate stack;    forming insulative sidewalls on at least one side of said at least one gatestack; and    selectively doping a plurality of regions in the substrate to a second conductivity type.    
   
   
       62 . The method of  claim 61 , further comprising the step of forming a transistor having a gatestack, the gatestack located at least partially under the thin transparent layer.  
   
   
       63 . The method of  claim 61 , further comprising the step of forming a second transparent conductive layer over the thin transparent layer.  
   
   
       64 . The method of  claim 63 , wherein the transparent conductive layer comprises indium tin oxide.  
   
   
       65 . The method of  claim 61 , wherein the substrate is doped p+ type and the step of selectively doping a plurality of region in the substrate utilizes n-type dopants.