Decoding circuit and decoding method for a Viterbi decoder

Abstract

The invention provides a decoding circuit and a decoding method for a Viterbi decoder. The decoding circuit of the Viterbi decoder includes a branch metric unit, an add-compare-select unit and a path memory unit. The path memory unit includes a data string controller, a trace write-in register array, an idling register array and a decoding register array. In this invention, a run length limited code is used for effectively solving the problem of generating a complicated trellis diagram after the trellis diagram of the Viterbi decoder is subjected to a longitudinal arrangement. In addition, the register array can perform other operations at different times. Accordingly, a high decoding speed of the Viterbi decoder can be achieved without requiring a lot of registers for data processing.

1 . A decoding circuit of a Viterbi decoder, the decoding circuit comprising a branch metric unit and an add-compare-select unit, the branch metric unit computing a branch metric value and outputting the branch metric value to the add-compare-select unit, wherein the add-compare-select unit comprising: 
 a plurality of adders, each adder receiving a branch metric value from the branch metric unit and an old path metric value to generate a new path metric;    a comparator for comparing the old path metrics to generate a selective signal; and    a multiplexer for receiving the new path metrics from the plurality of adders to output a decision bit according to the selective signal.