Command user interface with programmable decoder

Abstract

A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.

1 . A method for re-encoding a decoder, the method comprising: 
 changing only via locations in an insulating layer to effect re-encoding, wherein a via location defines a contact to which a gate of a transistor is coupled.    
   
   
       2 . The method of  claim 1 , wherein changing via locations comprises: 
 creating a revised via mask of the decoder for a new command; and    making vias through an insulating layer to create a transistor gate contact.    
   
   
       3 . The method of  claim 1 , wherein making vias comprises: 
 drilling vias through the insulating layer in response to the revised via mask; and    connecting appropriate vias to each gate of the plurality of series connected transistors.    
   
   
       4 . The method of  claim 3 , and further comprising: 
 connecting the gate of a first transistor of the plurality of series connected transistors to a supply voltage.    
   
   
       5 . The method of  claim 4 , wherein connecting the gate to the supply voltage changes the first transistor from a predetermined bit location to a do not care location.  
   
   
       6 . The method of  claim 3 , wherein drilling vias comprises: 
 drilling through the insulating layer to an appropriate signal bus of a plurality of signal buses.    
   
   
       7 . A memory device, comprising: 
 an array of memory cells;    control circuitry to read, write and erase the memory cells;    address circuitry to latch address signals provided on address input connections, and;    a command user interface connected to the ROM to control commands for the ROM, the CUI comprising: 
 a decoder having a plurality of series-connected transistors whose gates are selectively coupled to receive either an input or its complement using vias; and  
 a plurality of latches to latch input and output data for the command user interface.  
   
   
   
       8 . The memory device of  claim 7 , wherein at least one of the series-connected transistors is further selectively coupled to receive a supply voltage using its via.  
   
   
       9 . The memory device of  claim 7 , wherein using the vias comprises selecting a location for the via.  
   
   
       10 . The memory device of  claim 7 , wherein each series-connected transistor has a first contact hard wired to the input and a second contact hard wired to the complement of the input.  
   
   
       11 . The memory device of  claim 10 , wherein at least one of the transistors has a third contact hard wired to a supply voltage.  
   
   
       12 . The memory device of  claim 7 , wherein the decoder comprises: 
 a plurality of decoder blocks, each decoder block comprising a plurality of transistors connected in series, each transistor having a first contact coupled to the input, and a second contact coupled to the complement of the input.    
   
   
       13 . The memory device of  claim 7 , wherein each transistor is capable of one selective coupling to connect the gate of its transistor.  
   
   
       14 . The memory device of  claim 8 , wherein at least one of the plurality of transistors is further programmable to connect to the supply voltage to configure the transistor as a don't care.  
   
   
       15 . The memory device of  claim 7 , wherein the decoder comprises: 
 a first decoder section comprising: 
 a plurality of transistors connected in series; and  
 a plurality of contacts, each contact coupled to either the input or the complement of the input, wherein the vias connect a gate of a single transistor of the plurality of transistors to either the input or to the complement of the input using the vias.  
   
   
   
       16 . The memory device of  claim 15 , wherein at least one of the plurality of transistors is further selectively coupled to receive a supply voltage using its via.  
   
   
       17 . The memory device of  claim 15 , wherein the decoder further comprises a second decoder section substantially identical to the first decoder section, and connected in series with the first decoder section, the first and the second decoder sections to decode different inputs to the decoder.  
   
   
       18 . The memory device of  claim 15 , wherein the decoder further comprises a second decoder section substantially identical to the first decoder section, and connected in parallel with the first decoder section, the first and the second decoder sections to decode different inputs to the decoder.  
   
   
       19 . The memory device of  claim 7 , wherein the plurality of latches comprises: 
 a plurality of input latches to receive input data and a clock signal and to output latched input data to the decoder;    a plurality of output latches to receive output data from the ROM; and    a plurality of status latches to receive state information from the ROM and to output latched status data to the decoder.    
   
   
       20 . The memory device of  claim 19 , wherein the input latches further receive a feedback signal from an external write state machine and wherein the input latches output latched feedback data to external circuitry.  
   
   
       21 . A memory device, comprising: 
 an array of memory cells;    control circuitry to read, write and erase the memory cells;    address circuitry to latch address signals provided on address input connections, and;    a command user interface connected to the ROM to control commands for the ROM, the CUI comprising: 
 a plurality of transistors connected in series, each transistor having first and second contacts hard programmed to a low logic value and a high logic value respectively;  
 a plurality of vias each connectable between a gate of one of the plurality of transistors and the first or the second contact to hard program the low logic value or the high logic value; and  
 a plurality of latches to latch input and output data for the command user interface.  
   
   
   
       22 . The memory device of  claim 21 , wherein at least one of the plurality of transistors has a third contact hard programmed to a supply voltage.  
   
   
       23 . The memory device of  claim 21 , and further comprising: 
 a second plurality of transistors connected in series, each of the second plurality of transistors having first and second contacts hard programmed to a low logic value and a high logic value respectively;    a second plurality of vias each connectable between a gate of one of the second plurality of transistors and the first or the second contact to hard program the low logic value or the high logic value; and    a second plurality of latches to latch input and output data for the command user interface.    
   
   
       24 . A memory device, comprising: 
 an array of memory cells;    control circuitry to read, write and erase the memory cells;    address circuitry to latch address signals provided on address input connections, and;    a command user interface connected to the ROM to control commands for the ROM, the CUI comprising: 
 a plurality of decoders, each decoder having a series of transistors whose gates are selectively coupled to receive either an input or its complement using vias; and  
 a plurality of latches to latch input and output data for the command user interface.  
   
   
   
       25 . The memory device of  claim 24 , wherein each decoder comprises: 
 a plurality of transistors connected in series, each transistor having a first contact hard wired to the input and a second contact hard wired to the complement of the input.    
   
   
       26 . The memory device of  claim 24 , wherein each decoder further comprises a plurality of decoder section, each decoder section comprising: 
 a plurality of transistors connected in series; and    a plurality of contacts, each contact coupled to either the input or the complement of the input, wherein the vias connect a gate of a single transistor of the plurality of transistors to either the input or to the complement of the input using the vias.    
   
   
       27 . A memory device, comprising: 
 an array of non-volatile memory cells;    control circuitry to read, write and erase the memory cells;    address circuitry to latch address signals provided on address input connections, and;    a decoder connected to the array to control commands for the array, the decoder comprising:    a first decoder section comprising: 
 a plurality of transistors connected in series whose gates are selectively coupled to receive either an input or its complement from one of a pair of contacts; and  
 a pair of contacts for each transistor, each contact coupled to the input or to the complement of the input through a via.  
   
   
   
       28 . The memory device of  claim 27 , and further comprising an actuation transistor connected in series with the plurality of transistors, the actuation transistor enabling the plurality of transistors for a read of the plurality of transistors.  
   
   
       29 . The memory device of  claim 27 , wherein the plurality of transistors comprises the same number of transistors as there are data inputs to the decoder.  
   
   
       30 . The memory device of  claim 27 , wherein the first or the second contact is accessed by forming a via to the contact.  
   
   
       31 . The memory device of  claim 27 , wherein at least one of the series of transistors is further selectively coupled to receive a supply voltage.  
   
   
       32 . The memory device of  claim 27 , and further comprising: 
 a second decoder section comprising:    a second plurality of transistors connected in series whose gates are selectively coupled to receive either an input or its complement from one of a second pair of contacts; and    a pair of contacts for each of the plurality of second transistors, each of the second pairs of contacts coupled to the input or to the complement of the input.    
   
   
       33 . The memory device of  claim 32 , wherein the second decoder section is connected in series with the first decoder section.  
   
   
       34 . The memory device of  claim 32 , wherein the second decoder section is connected in parallel with the first decoder section.  
   
   
       35 . The memory device of  claim 34 , wherein each of the decoder sections decodes a particular different set of inputs.  
   
   
       36 . The memory device of  claim 32 , wherein at least one of the second plurality of transistors is further selectively coupled to receive a supply voltage using its via.  
   
   
       37 . The memory device of  claim 32 , and further comprising: 
 a third decoder section comprising:    a third plurality of transistors connected in series whose gates are selectively coupled to receive either an input or its complement from one of a third pair of contacts; and    a pair of contacts for each of the third plurality of transistors, each of the third pairs of contacts coupled to the input or to the complement of the input.    
   
   
       38 . The memory device of  claim 37 , wherein the third decoder section is connected in series with the first and the second decoder sections.  
   
   
       39 . The memory device of  claim 37 , wherein the third decoder section is connected in parallel with the first decoder and the second decoder sections.  
   
   
       40 . The memory device of  claim 37 , wherein each of the decoder sections decodes a particular different set of inputs to the decoder.  
   
   
       41 . The memory device of  claim 27 , wherein the first decoder section decodes data inputs to the programmable decoder.  
   
   
       42 . The memory device of  claim 32 , wherein the first decoder section decodes data inputs to the programmable decoder and wherein the second decoder section decodes status inputs to the programmable decoder.  
   
   
       43 . The memory device of  claim 37 , wherein the first decoder section decodes data inputs to the programmable decoder, and wherein the second decoder section decodes status inputs to the programmable decoder, and wherein the third decoder section decodes feedback inputs to the programmable decoder.  
   
   
       44 . The memory device of  claim 38 , wherein at least one of the third plurality of transistors is selectively coupled to a supply voltage.  
   
   
       45 . A memory device, comprising: 
 an array of non-volatile memory cells;    control circuitry to read, write and erase the memory cells;    address circuitry to latch address signals provided on address input connections, and;    a programmable decoder connected to the array to control commands for the array, the programmable decoder comprising:    a first decoder section coupled to decode data from the first input, the first decoder section comprising:    a plurality of transistors connected in series; and    a plurality of contacts, each contact coupled to either the input or the complement of the input, wherein the vias connect a gate of a single transistor of the plurality of transistors to either the input or to the complement of the input; and    a second decoder section substantially identical to the first decoder section, and connected in series with the first decoder section, the second decoder section coupled to decode data from the second input.    
   
   
       46 . The memory device of  claim 45 , and further comprising a plurality of latches to latch input and output data for the programmable decoder, wherein the plurality of latches comprises: 
 a plurality of input latches to receive input data and a clock signal and to output latched input data to the decoder;    a plurality of output latches to receive output data from a read only memory; and    a plurality of status latches to receive state information from the read only memory and to output latched status data to the decoder.