Clock generation apparatus

Abstract

A clock generation apparatus is provided with a frequency phase error calculation circuit 120, whereby a clock synchronized with burst lock and a line lock clock can be simultaneously generated by a DTO 121 on the basis of frequency information of a DTO 10 and phase error information from a phase comparator 7 and a digital LPF 8. Therefore, the clock generation apparatus can cope with a system that required plural clocks, and frequency spread is easily carried out by generating spread information by a frequency spread information generation circuit 90, and adding it in the DTO 121. As a result, interference to a video terminal from the clock can be reduced, and performance of a video terminal such as a television receiver can be exploited.

1 . A clock generation apparatus comprising: 
 an analog-to-digital converter (hereinafter referred to as an ADC) for converting a video signal on which a burst signal or a sync signal is superimposed, which is inputted through a video input terminal, into a digital signal, and outputting the digital signal;    a burst signal extraction circuit for receiving the video signal digitized by the ADC, and extracting the burst signal from the video signal;    a first phase comparator for comparing the phase of the burst signal extracted by the burst signal extraction circuit with the phase of a clock that operates the ADC;    a first digital low-pass filter (hereinafter referred to as a digital LPF) for receiving the output of the first phase comparator, and smoothing the output of the first phase comparator to output phase error information;    a horizontal sync signal separation circuit for receiving the video signal digitized by the ADC, and separating the horizontal sync signal from the video signal;    a second phase comparator for comparing the phase of the horizontal sync signal that is separated by the horizontal sync signal separation circuit with the phase of the clock that operates the ADC;    a second digital LPF for receiving the output of the second phase comparator, and smoothing the output of the second phase comparator to output phase error information;    a switch circuit for receiving the output of the digital LPF and the output of the second digital LPF, and selecting one of these outputs;    a digital timing oscillator (hereinafter referred to as a DTO) for receiving phase error information that is either the output of the first digital LPF or the output of the second digital LPF, which is outputted from the switch circuit, and outputting a digital timing signal which is generated at a timing according to the phase error information;    a digital-to-analog converter (hereinafter referred to as a DAC) for converting the digital timing signal outputted from the DTO into an analog signal, and outputting the analog signal; and    a PLL for supplying the ADC with a PLL clock according to the analog signal output from the DAC.    
   
   
       2 . A clock generation circuit comprising: 
 an ADC for converting a video signal on which a sync signal is superimposed, which is inputted through a video input terminal, into a digital signal, and outputting the digital signal;    a horizontal sync signal separation circuit for receiving the video signal digitized by the ADC, and separating the horizontal sync signal from the video signal;    a phase comparator for comparing the phase of the horizontal sync signal that is separated by the horizontal sync signal separation circuit with the phase of a clock that operates the ADC;    a digital LPF for receiving the output of the phase comparator, and smoothing the output of the phase comparator to output phase error information;    a stationary phase error addition circuit for receiving the phase error information from the digital LPF, and adding stationary phase error to the phase error information;    a DTO for receiving the phase error information outputted from the stationary phase error addition circuit, and outputting a digital timing signal that is generated at a timing according to the phase error information;    a DAC for converting the digital timing signal outputted from the DTO into an analog signal, and outputting the analog signal; and    a PLL for supplying the ADC with a PLL clock according to the analog signal output from the DAC.    
   
   
       3 . A clock generation circuit comprising: 
 a first ADC for converting a video signal on which a sync signal is superimposed or a sync signal, which is inputted through a first video signal input terminal, into a digital signal, and outputting the digital signal;    a second ADC for converting a video signal inputted through a second video signal input terminal into a digital signal, and outputting the digital signal;    a horizontal sync signal separation circuit for receiving the video signal or sync signal that is digitized by the first ADC, and separating the horizontal sync signal from the signal;    a phase comparator for comparing the phase of the horizontal sync signal that is separated by the horizontal sync signal separation circuit with the phase of a clock that operates the first ADC;    a digital LPF for receiving the output of the phase comparator, and smoothing the output of the phase comparator to output phase error information;    a stationary phase error addition circuit for receiving the phase error information from the digital LPF, and adding stationary phase error to the phase error information;    a DTO for receiving the phase error information outputted from the stationary phase error addition circuit, and outputting a digital timing signal that is generated at a timing according to the phase error information;    a DAC for converting the digital timing signal outputted from the DTO into an analog signal, and outputting the analog signal; and    a PLL for supplying the first ADC and the second ADC with a PLL clock according to the analog signal output from the DAC.    
   
   
       4 . A clock generation circuit comprising: 
 an ADC for converting a video signal on which a sync signal is superimposed, which is inputted through a video input terminal, into a digital signal, and outputting the digital signal;    a horizontal sync signal separation circuit for receiving the video signal digitized by the ADC, and separating the horizontal sync signal from the video signal;    a phase comparator for comparing the phase of the horizontal sync signal that is separated by the horizontal sync signal separation circuit with the phase of a clock that operates the ADC;    a stationary phase error addition circuit for adding stationary phase error to the phase error information outputted from the phase comparator;    a digital LPF for smoothing the output of the stationary phase error addition circuit;    a DTO for receiving the phase error information outputted from the digital LPF, and outputting a digital timing signal that is generated at a timing according to the phase error information;    a DAC for converting the digital timing signal outputted from the DTO into an analog signal, and outputting the analog signal; and    a PLL for supplying the ADC with a PLL clock according to the analog signal output from the DAC.    
   
   
       5 . A clock generation circuit comprising: 
 a first ADC for converting a video signal on which a sync signal is superimposed or a sync signal, which is inputted through a first video signal input terminal, into a digital signal, and outputting the digital signal;    a second ADC for converting a video signal inputted through a second video signal input terminal into a digital signal, and outputting the digital signal;    a horizontal sync signal separation circuit for receiving the video signal or sync signal that is digitized by the first ADC, and separating the horizontal sync signal from the signal;    a phase comparator for comparing the phase of the horizontal sync signal that is separated by the horizontal sync signal separation circuit with the phase of a clock that operates the first ADC;    a stationary phase error addition circuit for adding stationary phase error to the phase error information outputted from the phase comparator;    a digital LPF for smoothing the output of the stationary phase error addition circuit;    a DTO for receiving the phase error information outputted from the digital LPF, and outputting a digital timing signal that is generated at a timing according to the phase error information;    a DAC for converting the digital timing signal outputted from the DTO into an analog signal, and outputting the analog signal; and    a PLL for supplying the first ADC and the second ADC with a PLL clock according to the analog signal output from the DAC.    
   
   
       6 . A clock generation circuit comprising: 
 a first ADC for converting a video signal on which a sync signal is superimposed or a sync signal, which is inputted through a first video signal input terminal, into a digital signal, and outputting the digital signal;    a second ADC for converting a video signal inputted through a second video signal input terminal into a digital signal, and outputting the digital signal;    a horizontal sync signal separation circuit for receiving the video signal or sync signal that is digitized by the first ADC, and separating the horizontal sync signal from the signal;    a phase comparator for comparing the phase of the horizontal sync signal that is separated by the horizontal sync signal separation circuit with the phase of a clock that operates the first ADC;    a digital LPF for receiving the output of the phase comparator, and smoothing the output of the phase comparator to output phase error information;    a DTO for receiving the phase error information outputted from the digital LPF, and outputting a digital timing signal that is generated at a timing according to the phase error information;    a DAC for converting the digital timing signal outputted from the DTO into an analog signal, and outputting the analog signal;    a PLL for supplying the first ADC with a PLL clock according to the analog signal output from the DAC;    a delayed lock loop (hereinafter referred to as a DLL) for receiving the clock outputted from the PLL, and delaying the clock to output multiple-phase clocks; and    a clock selection circuit for selecting one of the multiple-phase clocks outputted from the DLL, and supplying the second ADC with the selected clock.    
   
   
       7 . A clock generation apparatus as defined in  claim 6  wherein 
 said DLL comprises a clock input terminal, N stages of variable delay elements for delaying a clock inputted through the clock input terminal, a phase comparator for comparing the outputs of the variable delay elements with a clock inputted through the clock input terminal, an LPF for smoothing the output of the phase comparator, a bias circuit for receiving the output of the LPF and controlling the delay values of the variable delay elements, and an output terminal for outputting the outputs of the N stages of variable delay elements.    
   
   
       8 . A clock generation circuit comprising: 
 a first ADC for converting a video signal on which a sync signal is superimposed or a sync signal, which is inputted through a first video signal input terminal, into a digital signal, and outputting the digital signal;    a second ADC for converting a video signal inputted through a second video signal input terminal into a digital signal, and outputting the digital signal;    a horizontal sync signal separation circuit for receiving the video signal or sync signal that is digitized by the first ADC, and separating the horizontal sync signal from the signal;    a phase comparator for comparing the phase of the horizontal sync signal that is separated by the horizontal sync signal separation circuit with the phase of a clock that operates the first ADC;    a digital LPF for receiving the output of the phase comparator, and smoothing the output of the phase comparator to output phase error information;    a DTO for receiving the phase error information outputted from the digital LPF, and outputting a digital timing signal that is generated at a timing according to the phase error information;    a DAC for converting the digital timing signal outputted from the DTO into an analog signal, and outputting the analog signal;    a multiple phase output PLL for multiplying the output of the DAC to supply a clock to the first ADC, and simultaneously, outputting an intermediate phase among the multiple phases; and    a clock selection circuit for selecting one of the multiple phase clocks outputted from the multiple phase output PLL, and supplying the second ADC with the selected clock.    
   
   
       9 . A clock generation apparatus as defined in  claim 8  wherein 
 said multiple phase output PLL comprises a ring oscillator comprising M stages of variable delay elements, a frequency divider for converting the frequency of the output of the ring oscillator to 1/K, a phase comparator for comparing the phase of the output from the frequency divider with the phase of an REF signal inputted through an REF signal input terminal, an LPF for receiving the output of the phase comparator, a bias circuit for receiving the output of the LPF, and controlling the delay values of the variable delay elements, and an output terminal for outputting the outputs of the M stages of variable delay elements.    
   
   
       10 . A clock generation circuit comprising: 
 an ADC for converting a video signal on which a sync signal is superimposed, which is inputted through a video input terminal, into a digital signal, and outputting the digital signal;    a horizontal sync signal separation circuit for receiving the video signal digitized by the ADC, and separating the horizontal sync signal from the video signal;    a phase comparator for comparing the phase of the horizontal sync signal that is separated by the horizontal sync signal separation-circuit with the phase of a clock that operates the ADC;    a digital LPF for receiving the output of the phase comparator, and smoothing the output of the phase comparator to output phase error information;    a first DTO for receiving the phase error information outputted from the digital LPF, and outputting a digital timing signal that is generated at a timing according to the phase error information;    a DAC for converting the digital timing signal outputted from the first DTO into an analog signal, and outputting the analog signal; and    a first PLL for supplying the first ADC with a PLL clock according to the analog signal output from the DAC;    a frequency spread information generation circuit for generating frequency spread information;    a second DTO for receiving the phase error information outputted from the digital LPF and the frequency spread information generated by the frequency spread information generation circuit, and outputting a digital timing signal;    a second DAC for converting the digital timing signal outputted from the second DTO into an analog signal; and    a PLL for outputting a PLL clock according to the analog signal output from the second DAC.    
   
   
       11 . A clock generation apparatus as defined in  claim 10  wherein 
 said frequency spread information generation circuit comprises a timing generation circuit which has a clock input terminal and counts the clocks inputted through the clock input terminal to generate a timing, and an up/down counter which receives a timing waveform generated by the timing generation circuit and switches between up counting and down counting.    
   
   
       12 . A clock generation circuit comprising: 
 an ADC for converting a video signal on which a sync signal is superimposed, which is inputted through a video input terminal, into a digital signal, and outputting the digital signal;    a horizontal sync signal separation circuit for receiving the video signal digitized by the ADC, and separating the horizontal sync signal from the video signal;    a phase comparator for comparing the phase of the horizontal sync signal that is separated by the horizontal sync signal separation circuit with the phase of a clock that operates the ADC;    a digital LPF for receiving the output of the phase comparator, and smoothing the output of the phase comparator to output phase error information;    a DTO for receiving the phase error information outputted from the digital LPF, and outputting a digital timing signal that is generated at a timing according to the phase error information;    a DAC for converting the digital timing signal outputted from the DTO into an analog signal, and outputting the analog signal; and    a first PLL for supplying the first ADC with a PLL clock according to the analog signal output from the DAC;    a second PLL for receiving the output of the DAC;    a frequency spread information generation circuit for generating frequency spread information;    a PWM circuit for converting the output of the frequency spread information generation circuit into an analog value;    an analog LPF for receiving the output of the PWM circuit; and    a resistor for adding the output of the analog LPF to a control voltage of a VCO which is a component of the second PLL.    
   
   
       13 . A clock generation apparatus as defined in  claim 12  wherein 
 said frequency spread information generation circuit comprises a timing generation circuit which has a clock input terminal and counts the clocks inputted through the clock input terminal to generate a timing, and an up/down counter which receives a timing waveform generated by the timing generation circuit and switches between up counting and down counting.    
   
   
       14 . A clock generation apparatus comprising: 
 an ADC for converting a video signal on which a burst signal or a sync signal is superimposed, which is inputted through a video input terminal, into a digital signal, and outputting the digital signal;    a burst signal extraction circuit for receiving the video signal digitized by the ADC, and extracting the burst signal from the video signal;    a first phase comparator for comparing the phase of the burst signal extracted by the burst signal extraction circuit with the phase of a clock that operates the ADC;    a first digital LPF for receiving the output of the first phase comparator, and smoothing the output of the first phase comparator to output phase error information;    a first DTO for receiving the phase error information outputted from the first digital LPF, and outputting a digital timing signal that is generated at a timing according to the phase error information;    a first DAC for converting the digital timing signal outputted from the first DTO into an analog signal, and outputting the analog signal;    a first PLL for supplying the ADC with a PLL clock according to the analog signal output from the first DAC;    a horizontal sync signal separation circuit for receiving the video signal digitized by the ADC, and separating a horizontal sync signal from the video signal;    a second phase comparator for comparing the phase of the horizontal sync signal separated by the horizontal sync signal separation circuit with the phase of the clock that operates the ADC;    a second digital LPF for receiving the output of the second phase comparator, and smoothing the output of the second phase comparator to output phase error information;    a frequency phase calculation circuit for receiving frequency information and phase information of the output of the first DTO and, the phase error information outputted from the second digital LPF, and outputting frequency information and phase information which are needed to generate a clock synchronized with the horizontal sync signal;    a second DTO for receiving the output of the frequency phase calculation circuit, and outputting a digital timing signal which is generated at a timing according to the output of the frequency phase calculation circuit;    a second DAC for converting the digital timing signal outputted from the second DTO into an analog signal, and outputting the analog signal; and    a second PLL for outputting a PLL clock according to an analog signal output from the second DAC.    
   
   
       15 . A clock generation apparatus as defined in  claim 14  wherein 
 said frequency phase calculation circuit comprises a line lock clock frequency information generation circuit for receiving phase error information between a burst lock clock and the horizontal sync signal, which is an output of the second digital LPF, and frequency information of a burst lock clock of the first DTO; and a line lock clock phase information generation circuit for receiving frequency information of a line lock clock outputted from the line lock clock frequency information generation circuit, phase information of the burst lock clock of the first DTO, the frequency information of the burst lock clock, and the phase error information between the burst lock clock and the horizontal sync signal.    
   
   
       16 . A clock generation apparatus as defined in  claim 15  wherein 
 said line lock clock frequency information generation circuit comprises a frequency ratio calculation circuit which receives the frequency division ratio of the burst lock clock to the horizontal sync signal during standard operation, the frequency division ratio of the line lock clock to the horizontal sync signal, and a phase difference between the actual horizontal sync signal and the signal obtained by frequency dividing the clock during burst lock clock standard operation, and calculates the ratio of frequencies between the burst lock clock and the line lock clock; and a multiplier which multiplies the frequency information of the burst lock clock by the ratio of the frequencies that is calculated by the frequency ratio calculation circuit to output frequency information of the line lock clock.    
   
   
       17 . A clock generation apparatus as defined in  claim 15  wherein 
 said line lock phase information generation circuit comprises a timing generation circuit for generating a timing for setting an initial value of the second DTO that generates the line lock clock, and a timing for capturing the phase information of the burst lock clock; a line lock/burst lock frequency ratio calculation circuit for calculating the ratio of frequencies from the burst lock frequency information and the line lock frequency information; and an initial value calculation circuit for calculating an initial value of the second DTO that generates the line lock clock from the phase difference between the actual horizontal sync signal and the signal obtained by frequency dividing the clock during burst lock clock standard operation, the phase information of the burst lock clock, and the frequency ratio obtained by the line lock/burst lock frequency ratio calculation circuit.    
   
   
       18 . A clock generation apparatus comprising: 
 an ADC for converting a video signal on which a burst signal or a sync signal is superimposed, which is inputted through a video input terminal, into a digital signal, and outputting the digital signal;    a burst signal extraction circuit for receiving the video signal digitized by the ADC, and extracting the burst signal from the video signal;    a first phase comparator for comparing the phase of the burst signal extracted by the burst signal extraction circuit with the phase of a clock that operates the ADC;    a first digital LPF for receiving the output of the first phase comparator, and smoothing the output of the first phase comparator to output phase error information;    a first DTO for receiving the phase error information outputted from the first digital LPF, and outputting a digital timing signal that is generated at a timing according to the phase error information;    a first DAC for converting the digital timing signal outputted from the first DTO into an analog signal, and outputting the analog signal;    a first PLL for supplying the ADC with a PLL clock according to the analog signal output from the first DAC;    a horizontal sync signal separation circuit for receiving the video signal digitized by the ADC, and separating a horizontal sync signal from the video signal;    a second phase comparator for comparing the phase of the horizontal sync signal separated by the horizontal sync signal separation circuit with the phase of the clock that operates the ADC;    a second digital LPF for receiving the output of the second phase comparator, and smoothing the output of the second phase comparator to output phase error information;    a frequency spread information generation circuit for generating frequency spread information;    a frequency phase calculation circuit for receiving frequency information and phase information of the output of the first DTO, and the phase error information outputted from the second digital LPF, and outputting frequency information and phase information which are needed to generate a clock synchronized with the horizontal sync signal;    a second DTO for receiving the output of the frequency phase calculation circuit and the output of the frequency spread information generation circuit, and outputting a digital timing signal;    a second DAC for converting the digital timing signal outputted from the second DTO into an analog signal, and outputting the analog signal; and    a second PLL for outputting a PLL clock according to an analog signal output from the second DAC.    
   
   
       19 . A clock generation apparatus as defined in  claim 18  wherein 
 said frequency spread information generation circuit comprises a timing generation circuit which has a clock input terminal and counts the clocks inputted through the clock input terminal to generate a timing, and an up/down counter which receives a timing waveform generated by the timing generation circuit and switches between up counting and down counting.    
   
   
       20 . A clock generation apparatus comprising: 
 an ADC for converting a video signal on which a burst signal or a sync signal is superimposed, which is inputted through a video input terminal, into a digital signal, and outputting the digital signal;    a burst signal extraction circuit for receiving the video signal digitized by the ADC, and extracting the burst signal from the video signal;    a first phase comparator for comparing the phase of the burst signal extracted by the burst signal extraction circuit with the phase of a clock that operates the ADC;    a first digital LPF for receiving the output of the first phase comparator, and smoothing the output of the first phase comparator to output phase error information;    a first DTO for receiving the phase error information outputted from the first digital LPF, and outputting a digital timing signal that is generated at a timing according to the phase error information;    a first DAC for converting the digital timing signal outputted from the first DTO into an analog signal, and outputting the analog signal;    a first PLL for supplying the ADC with a PLL clock according to the analog signal output from the first DAC;    a horizontal sync signal separation circuit for receiving the video signal digitized by the ADC, and separating a horizontal sync signal from the video signal;    a second phase comparator for comparing the phase of the horizontal sync signal separated by the horizontal sync signal separation circuit with the phase of the clock that operates the ADC;    a second digital LPF for receiving the output of the second phase comparator, and smoothing the output of the second phase comparator to output phase error information;    a frequency phase calculation circuit for receiving frequency information and phase information of the output of the first DTO, and the phase error information outputted from the second digital LPF, and outputting frequency information and phase information which are needed to generate a clock synchronized with the horizontal sync signal;    a second DTO for receiving the output of the frequency phase calculation circuit, and outputting a digital timing signal that is generated at a timing according to the output of the frequency phase calculation circuit;    a second DAC for converting the digital timing signal outputted from the second DTO into an analog signal, and outputting the analog signal;    a second PLL for receiving the output of the second-DAC;    a frequency spread information generation circuit for generating frequency spread information;    a PWM circuit for converting the output of the frequency spread information generation circuit into an analog value;    an analog LPF for receiving the output of the PWM circuit; and    a resistor for adding the output of the analog LPF to a control voltage of the VCO which is a component of the second PLL.    
   
   
       21 . A clock generation apparatus as defined in  claim 20  wherein 
 said frequency spread information generation circuit comprises a timing generation circuit which has a clock input terminal and counts the clocks inputted through the clock input terminal to generate a timing, and an up/down counter which receives a timing waveform generated by the timing generation circuit and switches between up counting and down counting.