Monitor pattern of semiconductor device and method of manufacturing semiconductor device

Abstract

A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.

1 . A monitor pattern of a semiconductor device, which is formed together with elements constituting the semiconductor device and detects presence of failure occurring in manufacturing steps, comprising: 
 a plurality of first resistive elements formed on a semiconductor substrate;    an interlayer insulation film which is formed on the semiconductor substrate and covers the first resistive elements;    a plurality of second resistive elements formed on the interlayer insulation film;    a plurality of contact vias buried in the interlayer insulation film, which connect the plurality of first resistive elements and the plurality of second resistive elements in series;    a dummy pattern which is formed in the same wiring layer as that of at least any one of the first resistive element and the second resistive element and is formed close to the resistive element.    
     
     
         2 . The monitor pattern of the semiconductor device according to  claim 1 , wherein the first and second resistive elements and the dummy pattern are formed by use of the same material as that of wirings connected to the semiconductor elements.  
     
     
         3 . The monitor pattern of the semiconductor device according to  claim 1 , wherein a space between the resistive elements and the dummy pattern is set equivalent to a minimum space between wirings, which is decided based on design criteria.  
     
     
         4 . The monitor pattern of the semiconductor device according to  claim 1 , wherein a space between the resistive elements and the dummy pattern is set in accordance with a minimum space between wirings of a chip formation portion.  
     
     
         5 . The monitor pattern of the semiconductor device according to  claim 1 , wherein an aspect ratio in etching between the resistive elements and the dummy pattern (a thickness of a resistive element material+a thickness of a mask material/a distance between a resistive element and a dummy pattern) is 3 or more.  
     
     
         6 . The monitor pattern of the semiconductor device according to  claim 1 , wherein the dummy pattern extends from a tip of the resistive element by ½ of a width of the resistive element or more.  
     
     
         7 . The monitor pattern of the semiconductor device according to  claim 1 , wherein the dummy pattern is formed in a lattice shape surrounding the plurality of resistive elements individually.  
     
     
         8 . The monitor pattern of the semiconductor device according to  claim 1 , wherein the dummy pattern is formed in a shape surrounding a tip of the resistive element from three directions and the resistive element and the dummy pattern overlap with each other by ½ of a width of the resistive element or more.  
     
     
         9 . The monitor pattern of the semiconductor device according to  claim 1 , wherein the contact vias are disposed at ends of the resistive element.  
     
     
         10 . The monitor pattern of the semiconductor device according to  claim 1 , wherein the contact vias are disposed at positions away inward from ends of the resistive elements by a specific distance.  
     
     
         11 . The monitor pattern of the semiconductor device according to  claim 1 , wherein the contact vias are disposed at positions shifted in a width direction of the resistive element from a center line of the resistive element.  
     
     
         12 . The monitor pattern of the semiconductor device according to  claim 1 , wherein the dummy pattern is constituted by a first cell in which the contact vias are disposed away inward from ends of the resistive element by a specific distance and at a position shifted in a width direction of the resistive element from a center line of the resistive element, a second cell in which the contact vias are disposed at the ends of the resistive element and at a position shifted in the width direction of the resistive element from the center line of the resistive element and a third cell in which the contact vias are disposed at the ends of the resistive element.  
     
     
         13 . The monitor pattern of the semiconductor device according to  claim 1 , wherein a center line of the resistive element obliquely intersects with an extension direction of a monitor pattern.  
     
     
         14 . A method of manufacturing a semiconductor device, comprising the steps of: 
 forming the monitor pattern according to  claim 1  in a region other than a chip formation portion of a semiconductor substrate together with formation of elements and    wirings constituting a semiconductor device;    electrically examining the monitor pattern; and    detecting abnormality of the wirings of the semiconductor device.