Fabrication of semiconductor dies with micro-pins and structures produced therewith
Abstract
A method for forming a semiconductor die, comprising forming a trench in a surface of the die; filing the trench with a sacrificial material; patterning the die to form a series of channels extending substantially perpendicularly to the trench; depositing a conductive material in the channels; removing at least a portion of the sacrificial material; and removing portions of the die under the trench so as to separate a portion of the die on one side of the trench from a portion on another side of the trench. The sacrificial material may be patterned so that the channels extend so as to be partially in a portion of the die and partially a portion of the sacrificial material. A series of structures are formed having dies with micro-pins.
Claims
exact text as granted — not AI-modified1 . A semiconductor die comprising:
a planar semiconductor member; and a plurality of conductive pins extending from said semiconductor member in a direction parallel to a plane of said semiconductor member.
2 . The semiconductor die of claim 1 , wherein said pins extend directly from said semiconductor member.
3 . The semiconductor die of claim 1 , wherein said semiconductor has a plurality of sides, and wherein said pins extend from at least one of said sides.
4 . The semiconductor die of claim 1 , wherein said semiconductor has a plurality of sides, and wherein said pins extend from all of said sides.
5 . The semiconductor die of claim 1 , wherein said pins are micro-pins having a of length of 1 to 1000 microns, a width of 1 to 500 microns and a depth of 1 to 800 microns in the direction into the die.
6 . The semiconductor die of claim 1 , wherein said semiconductor has a plurality of sides, and wherein said pins extend along said sides in a direction perpendicular to a plane of said semiconductor member.
7 . The semiconductor die of claim 6 , in combination with at least one additional semiconductor die, said semiconductor dies being disposed one over another so that respective pins of said semiconductor die are stacked one over another to facilitate electrical contact with one another.
8 . The combination of claim 7 , wherein said respective pins are diffusion bonded to one another to provide said electrical contact.
9 . The combination of claim 7 , further comprising an electrically conductive material disposed between said respective pins so as to provide said electrical contact.
10 . The combination of claim 7 , further comprising a substrate on which said combination is mounted.
11 . The combination of claim 10 , wherein said substrate is formed of a semiconductor material.
12 . The combination of claim 10 , further comprising a second substrate, said second substrate being formed of an insulating material.
13 . The semiconductor die of claim 1 , in combination with at least one other semiconductor die of claim 1 , successive ones of said semiconductor dies being assembled with at least one wiring substrate between dies, said at least one wiring substrate providing electrical connections between said dies.
14 . The combination of claim 13 , wherein said dies and said at least one substrate are assembled so as to form a solid rectangle.
15 . The combination of claim 14 , further comprising at least one additional semiconductor die assembled to the outside of said solid rectangle, said additional semiconductor die having electrical connections to at least one of said dies in said solid rectangle.
16 . The combination of claim 13 , wherein said wiring substrates have openings therein to facilitate management of heat.
17 . A semiconductor die comprising:
a planar semiconductor member; and a plurality of first electrically conductive pins formed on a surface of said semiconductor member, said pins having portions extending along a side of said semiconductor member.
18 . The semiconductor member of claim 17 , in combination with:
a second semiconductor member having second electrically conductive pins formed on a surface of said second semiconductor member, said second pins having portions extending along a side of said second semiconductor member, at least a portion of said first pins and said second pins being disposed on said semiconductor members so as to align with one another when said semiconductor members are placed in close proximity to one another, so that electrical contact between respective ones of said first pins and said second pins is facilitated.
19 . The combination of claim 18 , further comprising at least one additional semiconductor member, said additional semiconductor member having additional pins, said additional pins having portions extending along a side of said additional semiconductor member, said additional pins being disposed on said additional semiconductor member so as to align with additional pins on an additional side of said first semiconductor member or said second semiconductor member when said additional semiconductor member is placed in close proximity to said first semiconductor member or said second semiconductor, so that electrical contact between respective ones of said additional pins and said first pins or second pins is facilitated.
20 . The combination of claim 19 , wherein said semiconductor members are disposed so as to be coplanar.
21 . A semiconductor die substrate comprising:
a planar semiconductor member, said member having a plurality of micro-cups formed on a surface thereof, at least a portion of said micro-cups being sized, shaped and positioned so as to receive micro-pins.
22 . The semiconductor die of claim 21 , in combination with:
a second semiconductor die, said second semiconductor die comprising:
a planar semiconductor member;
a plurality of conductive micro-pins extending from said semiconductor member in a direction parallel to a plane of said semiconductor member,
said micro-pins being received in said micro-cups.
23 . The combination of claim 22 , wherein said semiconductor die substrate and said second semiconductor die are perpendicular to one another.
24 . The combination of claim 22 , further comprising at least one bracket member, said bracket member having a first surface in contact with said semiconductor die substrate and a second surface in contact with said second semiconductor die.
25 . The combination of claim 22 , further comprising an adhesive material disposed between said semiconductor members to facilitate said semiconductor members being secured to one another.
26 .- 38 . (canceled)Join the waitlist — get patent alerts
Track US2006081976A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.