Aspect ratio controlled etch selectivity using time modulated DC bias voltage

Abstract

A modulated bias power etching method for etching a substrate is disclosed. The method alternatively deposits and etches material from a low aspect area of an integrated circuit device to form a static area while etching material from a high aspect area. The modulation pulse period and repetition rate are adjusted to permit deposition at low aspect ratio and very little or no deposition at high aspect ratio during the deposition cycle and to permit etching of the material deposited on the low aspect ratio area and etching of the material in the high aspect ratio area during the etching cycle.

1 - 35 . (canceled)  
   
   
       36 . An integrated circuit device wherein said device is selectively etched by a method, comprising: 
 placing said device into a reactive chamber;    introducing into said chamber an etching gas;    providing a DC bias voltage to said substrate; and    modulating said DC bias voltage from a first voltage to a second voltage for a predetermined pulsing period to selectively etch said device.    
   
   
       37 . The device according to  claim 36 , wherein said method includes controlling deposition on a first position of a first material having a first aspect ratio while continuously etching a second position of a second material with a second aspect ratio, wherein said first aspect ratio is less than said second aspect ratio.  
   
   
       38 . The device according to  claim 37 , wherein said first aspect ratio is less than or equal to 5.  
   
   
       39 . The device according to  claim 37 , wherein said second aspect ratio is greater than or equal to 3.  
   
   
       40 . The device according to  claim 38 , wherein said first aspect ratio is from about 0.5 to about 5.0.  
   
   
       41 . The device according to  claim 39 , wherein said second aspect ratio is from about 3.0 to about 20.0.  
   
   
       42 . The device according to  claim 36 , wherein said etching gas includes a fluorocarbon gas.  
   
   
       43 . The device according to  claim 36 , wherein said etching gas includes a hydcrofluorocarbon gas.  
   
   
       44 . The device according to  claim 36 , wherein said etching gas includes a gas selected from the group consisting of CF4, C2F6, C3F8, C4F8 and CHF3.  
   
   
       45 . The device according to  claim 43 , wherein said etching gas includes CHF3.  
   
   
       46 . The device according to  claim 36 , wherein said device includes a self-aligned contact etched thereon.  
   
   
       47 . The device according to  claim 36 , wherein said bias voltage is modulated on a duty cycle of from about 10% to about 90%  
   
   
       48 . The device according to  claim 36 , wherein said modulated DC bias voltage is obtained by modulating a source power.  
   
   
       49 . The device according to  claim 36 , wherein said modulated DC bias voltage is obtained by modulating a source power, a bias power or combinations thereof.  
   
   
       50 . The device according to  claim 36 , wherein said predetermined pulsing period is calculated according to a first relative deposition rate and a first relative etch rate of said first material, and to a second relative deposition rate and a second relative etch rate of said second material.  
   
   
       51 . The device according to  claim 36 , wherein said bias voltage is modulated between about 0 volts and about 300 volts.  
   
   
       52 . The device according to  claim 51 , wherein said bias voltage is modulated between about 10 volts and about 80 volts.  
   
   
       53 - 63 . (canceled)  
   
   
       64 . A method of forming an integrated circuit device comprising: 
 forming at least one layer of material to be etched over a substrate;    forming an opening in said at least one layer of material; and    applying a plasma-inducing voltage to said device to deposit a protective layer of material at a first portion of said opening having a first aspect ratio while concurrently etching a second portion of said opening having a second aspect ratio.    
   
   
       65 . The method according to  claim 64  wherein said first aspect ratio is smaller than said second aspect ratio.  
   
   
       66 . The method according to  claim 64  wherein said first aspect ratio is from about 0.5 to about 5.0.  
   
   
       67 . The method according to  claim 64  wherein said protective layer is formed over a gate stack.  
   
   
       68 . The method according to  claim 64  wherein said second aspect ratio is from about 3.0 to about 20.0.  
   
   
       69 . The method according to  claim 64  further comprising alternating said voltage between at least a first voltage value and a second voltage value different from said first voltage value.  
   
   
       70 . A method of protecting a structure in an integrated circuit during etching comprising: 
 forming an opening over at least a portion of the structure to be protected; and    applying a plasma-inducing voltage to said integrated circuit whereby a protective layer is deposited onto a first area of said opening which is over said portion of the structure to be protected, while a second area of said opening is continuously etched.    
   
   
       71 . The method according to  claim 70  wherein said structure to be protected is a gate stack.  
   
   
       72 . The method according to  claim 70  wherein said first area has a first aspect ration and said second area has a second aspect ratio.  
   
   
       73 . The method according to  claim 72  wherein said first aspect ratio is smaller than said second aspect ratio.  
   
   
       74 . The method according to  claim 70  further comprising alternating said voltage between at least a first voltage value and a second voltage value different from said first voltage value.