Non-volatile electrically alterable memory cells for storing multiple data

Abstract

A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

1 . An electrically alterable non-volatile memory string, comprising: 
 a plurality of memory devices, each memory device having a control transistor capable of storing a plurality of data, the plurality of memory devices having a first end and a second end;    a first select transistor connected to the first end;    a second select transistor connected to the second end; and    a connector connecting the first select transistor to a bit line.    
     
     
         2 . The memory string of  claim 1 , wherein the first select transistor being further connected to the second select transistor of an adjacent memory string.  
     
     
         3 . The memory string of  claim 1 , wherein the control transistor being capable of storing data representing four logic states.  
     
     
         4 . The memory string of  claim 1 , wherein the control transistor being capable of storing data representing multiple logic states.  
     
     
         5 . The memory device of  claim 1 , wherein one memory device being connected to an adjacent memory device, whereby a drain of one memory device being connected to a source of an adjacent device.  
     
     
         6 . An electrically alterable non-volatile memory string comprising: 
 A plurality of memory devices, each memory device having a control transistor capable of storing a plurality of data, each memory device having a first end and a second end;    a first diffusion region connected to the first end of each memory device;    a second diffusion region, spaced-apart from the first diffusion region, connected to the second end of each memory device; and    a plurality of connectors connecting the control transistor of each memory device to a bit line.    
     
     
         7 . The memory string of  claim 6 , wherein the control transistor being capable of storing data representing four logic states.  
     
     
         8 . The memory string of  claim 6 , wherein the control transistor being capable of storing data representing multiple logic states.  
     
     
         9 . The memory string of  claim 6 , wherein the memory devices are connected in parallel to each other between the first diffusion region and the second diffusion region.