Trench in semiconductor device and formation method thereof
Abstract
A method of forming a trench in a semiconductor device includes forming a sacrificial layer on a silicon wafer and selectively etching the sacrificial layer to form a LOCOS opening having a predetermined width. Thermal oxidation is performed on a portion of the silicon wafer exposed through the LOCOS opening to form a LOCOS oxide layer. Also, etching is performed on the LOCOS oxide layer and the silicon wafer to a desired depth to form a trench. During this process, etching is performed such that the LOCOS oxide layer is left remaining on the silicon wafer at an area corresponding to edges of the trench. An insulation layer is deposited such that the trench is filled with a material of the insulation layer. The present invention also provides a trench in a semiconductor device used as a device isolation region formed in a silicon wafer. Upper corner areas of the silicon wafer adjacent to the trench are rounded, and a LOCOS oxide layer is formed on the corner areas.
Claims
exact text as granted — not AI-modified1 . A trench in a semiconductor device used as a device isolation region formed in a silicon wafer, in which upper corner areas of the silicon wafer adjacent to the trench are rounded, and a LOCOS oxide layer is formed on the corner areas.
2 . The trench of claim 1 , wherein a liner oxide layer is formed on inner walls of the trench and on the LOCOS oxide layer.
3 . The trench of claim 2 , wherein the liner oxide layer is formed to a thickness of 100-500 Å.
4 . The trench of claim 1 , wherein the LOCOS oxide layer is formed to a thickness of at most 200 Å.
5 . The trench of claim 4 , wherein a liner oxide layer is formed along inner walls of the trench and on the LOCOS oxide layer, to a thickness of 100-500 Å.
6 . A device isolation region in a silicon wafer, comprising:
a trench in the silicon wafer, rounded upper corner areas of the silicon wafer adjacent to the trench, and a LOCOS oxide layer on the rounded upper corner areas.
7 . The device isolation region of claim 6 , further comprising a liner oxide layer on inner walls of the trench and on the LOCOS oxide layer.
8 . The device isolation region of claim 7 , wherein the liner oxide layer has a thickness of 100-500 Å.
9 . The device isolation region of claim 6 , wherein the LOCOS oxide layer has a thickness of at most 200 Å.
10 . The device isolation region of claim 9 , further comprising a liner oxide layer along inner walls of the trench and on the LOCOS oxide layer, having a thickness of 100-500 Å.
11 . The device isolation region of claim 6 , wherein the LOCOS oxide layer on the rounded upper corner areas has a width of at most 200 Å.
12 . The device isolation region of claim 6 , further comprising an insulation layer in the trench.
13 . The device isolation region of claim 7 , further comprising an insulation layer on the liner oxide layer in the trench.
14 . A device isolation region, comprising:
trench in a silicon wafer; rounded upper corner areas of the silicon wafer adjacent to the trench; and a liner oxide layer on inner walls of the trench and on the rounded upper corner areas; and an insulation layer filling the trench.
15 . The device isolation region of claim 14 , further comprising.
16 . The device isolation region of claim 14 , wherein the liner oxide layer has a thickness of 100-500 Å.
17 . The device isolation region of claim 14 , wherein the rounded upper corner areas have a width of at most 200 Å.
18 . A semiconductor device, comprising the device isolation region of claim 14.Join the waitlist — get patent alerts
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