Lead frame assemblies and decoupling capacitors

Abstract

A lead frame assembly includes at least two layers, each including an electrically conductive bus and a group of leads that extend substantially from a first edge of the assembly. The leads of each layer may include portions that extend in substantially the same direction. The electrically conductive buses are at least partially superimposed with respect to one another. Leads of one of the layers may be arranged in groups which flank the remainder of the lead of another layer. A dielectric element is disposed at least partially between the layers; for example, between at least portions of the superimposed regions of the buses. One of the buses may be connectable to a power supply source (V cc ), while the other may be connectable to a power supply ground (V ss ). In such an arrangement, the mutually superimposed regions of the buses may form a decoupling capacitor.

1 . A lead frame assembly, comprising: 
 a first layer including: 
 at least a portion of a first electrically conductive bus; and  
 a first group of leads including a first plurality of leads, at least one of which extends from a first edge of the lead frame assembly;  
   a second layer including: 
 at least a portion of a second electrically conductive bus, the second bus being at least partially superimposed with respect to the first bus; and  
 a second group of leads including a second plurality of leads, at least one of which extends from the first edge of the lead frame assembly; and  
   a dielectric element located between portions of the first and second layers.    
     
     
         2 . The lead frame assembly of  claim 1 , wherein the first group of leads is located substantially centrally along an edge of the semiconductor device assembly and the second group of leads is located laterally adjacent to the first group of leads.  
     
     
         3 . The lead frame assembly of  claim 1 , comprising two second groups of leads positioned on opposite sides of the first group of leads.  
     
     
         4 . The lead frame assembly of  claim 1 , wherein at least one of the first and second buses is electrically connected to a lead finger of the first and second groups.  
     
     
         5 . The lead frame assembly of  claim 1 , wherein the dielectric element is positioned at least partially between superimposed portions of the first and second electrically conductive buses.  
     
     
         6 . The lead frame assembly of  claim 5 , wherein superimposed portions of the first electrically conductive bus, the dielectric element, and the second electrically conductive bus comprise a capacitor.  
     
     
         7 . The lead frame assembly of  claim 1 , wherein superimposed portions of the first layer, the dielectric element, and the second layer comprise a capacitor.  
     
     
         8 . The lead frame assembly of  claim 1 , further comprising: 
 another dielectric element located on at least one of the first and second layers, opposite from the dielectric element.    
     
     
         9 . The lead frame assembly of  claim 8 , wherein the another dielectric element comprises an adhesive material.  
     
     
         10 . The lead frame assembly of  claim 8 , wherein the another dielectric element is configured to be positioned between the lead frame assembly and a semiconductor device.  
     
     
         11 . The lead frame assembly of  claim 1 , wherein leads of the first plurality of leads include portions that are oriented substantially parallel to one another.  
     
     
         12 . The lead frame assembly of  claim 11 , wherein leads of the second plurality of leads include portions that are oriented substantially parallel to one another.  
     
     
         13 . The lead frame assembly of  claim 1 , wherein the first and second layers mutually define the first edge of the lead frame assembly.  
     
     
         14 . The lead frame assembly of  claim 13 , wherein the leads of the first and second pluralities of leads extend from the first edge.  
     
     
         15 . The lead frame assembly of  claim 14 , wherein the leads of the first and second pluralities of leads include portions that are oriented substantially parallel to one another.  
     
     
         16 . A decoupling capacitor, comprising: 
 a first layer including: 
 at least a portion of a first electrically conductive bus; and  
 a first group of leads including a first plurality of leads;  
   a second layer including: 
 at least a portion of a second electrically conductive bus, the second bus being at least partially superimposed with respect to the first bus; and  
 a second group of leads including a second plurality of leads; and  
   a dielectric element located at least partially between superimposed regions of the first and second electrically conductive buses.    
     
     
         17 . The decoupling capacitor of  claim 16 , wherein the first group of leads is located substantially centrally along an edge of the semiconductor device assembly and the second group of leads is located laterally adjacent to the first group of leads.  
     
     
         18 . The decoupling capacitor of  claim 16 , comprising two second groups of leads positioned on opposite sides of the first group of leads.  
     
     
         19 . The decoupling capacitor of  claim 16 , wherein at least one of the first and second buses is electrically connected to a lead finger of the first and second groups.  
     
     
         20 . The decoupling capacitor of  claim 16 , further comprising: 
 another dielectric element located on an exposed surface of at least one of the first layer and the second layer configured to separate the first or second layer from a semiconductor device.    
     
     
         21 . The decoupling capacitor of  claim 20 , wherein the another dielectric element is configured to separate the first or second layer from a semiconductor device.  
     
     
         22 . The decoupling capacitor of  claim 20 , wherein the another dielectric element comprises an adhesive material.  
     
     
         23 . The decoupling capacitor of  claim 20 , wherein the another dielectric element is configured to secure the decoupling capacitor to the semiconductor device.  
     
     
         24 . The decoupling capacitor of  claim 16 , wherein leads of the first plurality of leads include portions that are oriented substantially parallel to one another.  
     
     
         25 . The decoupling capacitor of  claim 24 , wherein leads of the second plurality of leads include portions that are oriented substantially parallel to one another.  
     
     
         26 . The decoupling capacitor of  claim 16 , wherein the first and second layers mutually define a common edge of the decoupling capacitor.  
     
     
         27 . The decoupling capacitor of  claim 26 , wherein the leads of the first and second pluralities of leads extend from the common edge.  
     
     
         28 . The decoupling capacitor of  claim 27 , wherein the leads of the first and second pluralities of leads are oriented substantially parallel to one another.