Apparatus and methods for adjusting performance characteristics of programmable logic devices

Abstract

A programmable logic device (PLD) includes a circuit that controls a supply voltage of at least a portion of the circuitry within the PLD (such as a block, a sub-block, or a region). The circuit also filters noise within the PLD. Controlling the supply voltage allows trading off various performance characteristics, such as speed and power consumption.

1 . A programmable logic device (PLD), comprising a first circuit configured to control a supply voltage of a second circuit, the first circuit further configured to filter noise within the programmable logic device (PLD).  
     
     
         2 . The programmable logic device (PLD) according to  claim 1 , wherein the first circuit comprises a variable impedance device, the variable impedance device configured to provide the supply voltage of the second circuit.  
     
     
         3 . The programmable logic device (PLD) according to  claim 1 , wherein the transistor comprises a native transistor of the programmable logic device.  
     
     
         4 . The programmable logic device (PLD) according to  claim 2 , wherein the variable impedance device is further configured to provide the supply voltage of the second circuit in response to a programmable logic device (PLD) configuration datum.  
     
     
         5 . The programmable logic device (PLD) according to  claim 2 , wherein the variable impedance device comprises a transistor.  
     
     
         6 . The programmable logic device (PLD) according to  claim 3 , wherein the first circuit further comprises a control circuit coupled to a gate terminal of the transistor.  
     
     
         7 . The programmable logic device (PLD) according to  claim 6 , wherein the transistor adjusts the supply voltage of the second circuit in response to an output signal of the control circuit.  
     
     
         8 . The programmable logic device (PLD) according to  claim 4 , wherein the first circuit further comprises a first capacitor coupled to a gate terminal of the transistor.  
     
     
         9 . The programmable logic device (PLD) according to  claim 4 , wherein the first circuit further comprises a second capacitor coupled to a source terminal of the transistor.  
     
     
         10 . The programmable logic device (PLD) according to  claim 7 , wherein the output signal of the control circuit is derived from information received from an information source external to the programmable logic device (PLD).  
     
     
         11 . The programmable logic device (PLD) according to  claim 6 , wherein the output signal of the control circuit depends on a power consumption of a circuit within the programmable logic device (PLD).  
     
     
         12 . The programmable logic device (PLD) according to  claim 1 , wherein the second circuit comprises a programmable logic circuit.  
     
     
         13 . The programmable logic device (PLD) according to  claim 12 , wherein the programmable logic circuit comprises one of a plurality of programmable logic circuits arranged as a two-dimensional array.  
     
     
         14 . The programmable logic device (PLD) according to  claim 12 , wherein the programmable logic circuit comprises a logic element.  
     
     
         15 . The programmable logic device (PLD) according to  claim 14 , wherein the programmable logic circuit comprises local interconnect circuitry.  
     
     
         16 . The programmable logic device (PLD) according to  claim 1 , wherein the second circuit comprises programmable interconnect circuitry.  
     
     
         17 . The programmable logic device (PLD) according to  claim 1 , wherein the second circuit comprises configuration memory configured to store configuration data of the programmable logic device (PLD).  
     
     
         18 . A programmable logic device (PLD), comprising: 
 a first circuit, the first circuit residing in a first deep n-well; and    a first variable impedance device coupled to the first circuit, the first variable impedance device configured to adjust a supply voltage of the first circuit.    
     
     
         19 . The programmable logic device (PLD) according to  claim 18 , further comprising a first capacitor coupled to the first variable impedance device.  
     
     
         20 . The programmable logic device (PLD) according to  claim 18 , comprising: 
 a second circuit, the second circuit residing in a second deep n-well; and    a second variable impedance device coupled to the second circuit, the second variable impedance device configured to adjust a supply voltage of the second circuit.    
     
     
         21 . The programmable logic device (PLD) according to  claim 20 , further comprising a second capacitor coupled to the second variable impedance device.  
     
     
         22 . The programmable logic device (PLD) according to  claim 20 , wherein the first circuit is relatively sensitive to noise.  
     
     
         23 . The programmable logic device (PLD) according to  claim 20 , wherein the first circuit comprises analog circuitry.  
     
     
         24 . The programmable logic device (PLD) according to  claim 20 , wherein the first circuit comprises mixed-mode circuitry.  
     
     
         25 . The programmable logic device (PLD) according to  claim 22 , wherein the second circuit generates relatively high levels of noise.  
     
     
         26 . The programmable logic device (PLD) according to  claim 20 , wherein the first variable impedance device derives the supply voltage of the first circuit from a first voltage supplied to the programmable logic device (PLD).  
     
     
         27 . The programmable logic device (PLD) according to  claim 20 , wherein the first variable impedance device derives the supply voltage of the first circuit from a first voltage, wherein the first voltage is derived within the programmable logic device (PLD) from a second voltage supplied to the programmable logic device (PLD).  
     
     
         28 . A method of configuring a programmable logic device (PLD) to implement an electronic circuit, the method comprising: 
 mapping the electronic circuit to functional resources within the programmable logic device (PLD) to generate a circuit to be implemented by the programmable logic device (PLD);    identifying at least one critical circuit path in the circuit to be implemented by the programmable logic device (PLD); and    setting a supply voltage level of at least a portion of the critical circuit path.    
     
     
         29 . The method according to  claim 28 , wherein setting a supply voltage level of at least a portion of the critical circuit path further comprises programming a configuration memory (CRAM) of the programmable logic device (PLD).  
     
     
         30 . The method according to  claim 29 , wherein setting a supply voltage level of at least a portion of the critical circuit path further comprises adjusting an impedance of a variable impedance device depending on a value programmed in the configuration memory (CRAM).  
     
     
         31 . The method according to  claim 28 , further comprising adjusting the supply voltage level of at least a portion of the critical circuit path.  
     
     
         32 . The method according to  claim 31 , wherein adjusting the supply voltage level of at least a portion of the critical circuit path further comprises trading off speed and power consumption of the at least a portion of the critical circuit path.  
     
     
         33 . The method according to  claim 28 , wherein setting a supply voltage level of at least a portion of the critical circuit path further comprises using an output signal of a control circuit.  
     
     
         34 . The method according to  claim 33 , wherein setting a supply voltage level of at least a portion of the critical path further comprises adjusting an impedance of a variable impedance device by using the output signal of the control circuit.  
     
     
         35 . A method of operating a programmable logic device (PLD), the method comprising: 
 setting a supply voltage level of a first circuit in the programmable logic device (PLD) to a first level;    determining whether a performance measure of the programmable logic device (PLD) meets a criterion; and    adjusting the supply voltage level of the first circuit depending on whether the performance measure of the programmable logic device (PLD) meets the criterion.    
     
     
         36 . The method according to  claim 35 , wherein determining whether a performance measure of the programmable logic device (PLD) meets a criterion further comprises obtaining the performance measure.  
     
     
         37 . The method according to  claim 36 , wherein obtaining the performance measure further comprises sensing a quantity within the programmable logic device (PLD).  
     
     
         38 . The method according to  claim 37 , wherein sensing a quantity within the programmable logic device (PLD) further comprises sensing a temperature.  
     
     
         39 . The method according to  claim 35 , wherein adjusting the supply voltage level of the first circuit further comprises: 
 leaving the supply voltage level of the first circuit unchanged if the performance measure of the programmable logic device (PLD) meets the criterion; and    changing the supply voltage level of the first circuit to a second level if the performance measure of the programmable logic device (PLD) fails to meet the criterion.    
     
     
         40 . The method according to  claim 35 , wherein the performance measure comprises a speed of operation of the first circuit.  
     
     
         41 . The method according to  claim 35 , wherein the performance measure comprises a power consumption of the first circuit.  
     
     
         42 . The method according to  claim 35 , wherein setting a supply voltage level of a first circuit in the programmable logic device (PLD) to a first level further comprises setting the supply voltage to a level derived from information received from a source external to the programmable logic device.  
     
     
         43 . The method according to  claim 35 , wherein setting a supply voltage level of a first circuit in the programmable logic device (PLD) to a first level further comprises setting the supply voltage to a level specified by configuration data of the programmable logic device (PLD).  
     
     
         44 . The method according to  claim 35 , further comprising using a feedback circuit to determine if the performance measure of the programmable logic device (PLD) meets the criterion.  
     
     
         45 . A method of operating a programmable logic device (PLD) configured to function in an operating environment, the method comprising: 
 setting a supply voltage level of a first circuit in the programmable logic device (PLD) to a first level; and    adjusting the supply voltage level of the first circuit depending on at least one characteristic of the operating environment of the programmable logic device (PLD).    
     
     
         46 . The method according to  claim 45 , wherein adjusting the supply voltage level of the first circuit further comprises adjusting the supply voltage level of the first circuit to a second level if the at least one characteristic of the operating environment indicates that a performance of the first circuit should be changed.  
     
     
         47 . The method according to  claim 46 , wherein adjusting the supply voltage level of the first circuit further comprises increasing an operating speed of the first circuit if the at least one characteristic of the operating environment indicates that a performance of the first circuit should be increased.  
     
     
         48 . The method according to  claim 47 , wherein adjusting the supply voltage level of the first circuit further comprises trading off the operating speed of the first circuit with a power consumption of the first circuit.  
     
     
         49 . The method according to  claim 46 , wherein adjusting the body-bias level of the at least one transistor further comprises decreasing an operating speed of the first circuit if the at least one characteristic of the operating environment indicates that a performance of the first circuit should be decreased.