Adaptive cache algorithm for temperature sensitive memory

Abstract

A temperature sensitive memory, such as a ferro-electric polymer memory, may be utilized as a disk cache memory in one embodiment. If the temperature begins to threaten shutdown, the memory may be transitioned from a write-back to a write-through cache memory. In such case, the system is ready for shutdown without the loss of critical data.

1 . A method comprising: 
 monitoring a temperature; and    in response to a detection of a temperature condition, operating a cache memory in one of two different modes depending on the temperature.    
   
   
       2 . The method of  claim 1  including monitoring the temperature of a ferroelectric polymer cache memory.  
   
   
       3 . The method of  claim 1  including adjusting the operation of a system using said memory at a first temperature and, in response to the detection of a higher, second temperature, transitioning the cache from a write-back cache to a write-through cache.  
   
   
       4 . The method of  claim 3 , including slowing an operation of said system at said first temperature.  
   
   
       5 . The method of  claim 3  including reducing pre-fetching at said first temperature.  
   
   
       6 . A computer readable medium storing instructions that, if executed, enable a processor-based system to: 
 monitor a temperature of a cache memory; and    in response to the detection of a temperature condition, operating a cache memory in one of two different modes depending on the temperature.    
   
   
       7 . The medium of  claim 6  further storing instructions that, if executed, enable a processor-based system to monitor the temperature of a ferroelectric polymer cache memory.  
   
   
       8 . The medium of  claim 6  further storing instructions that, if executed, enable a processor-based system to adjust the operation of a system using said memory at a first temperature and, in response to the detection of a higher, second temperature, transition the cache memory from a write-back to a write-through cache.  
   
   
       9 . A circuit comprising: 
 a cache memory; and    a component to receive an indication of a temperature and to develop a signal to transition the cache memory from a first to a second operating mode in response to said temperature indication.    
   
   
       10 . The circuit of  claim 9  wherein said component to vary the operation of a system to adjust for the temperature affected operation of said cache memory.  
   
   
       11 . The circuit of  claim 10  wherein said component to adjust a caching operation of the system in response to a temperature indication from said memory.  
   
   
       12 . The circuit of  claim 10  wherein said component to shut off said cache in response to a temperature indication.  
   
   
       13 . The circuit of  claim 12  wherein said component to invalidate a cache line in said cache memory.  
   
   
       14 . The circuit of  claim 9  including a ferroelectric polymer memory.